Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	411862754	0	0	0
ctrl_rd_A	411862754	748	0	0
host_fifo_config_rd_A	411862754	6385	0	0
host_nack_handler_timeout_rd_A	411862754	494	0	0
host_timeout_ctrl_rd_A	411862754	545	0	0
intr_enable_rd_A	411862754	2004	0	0
ovrd_rd_A	411862754	1821	0	0
target_fifo_config_rd_A	411862754	595	0	0
target_id_rd_A	411862754	664	0	0
target_timeout_ctrl_rd_A	411862754	468	0	0
timeout_ctrl_rd_A	411862754	667	0	0
timing0_rd_A	411862754	512	0	0
timing1_rd_A	411862754	519	0	0
timing2_rd_A	411862754	563	0	0
timing3_rd_A	411862754	514	0	0
timing4_rd_A	411862754	420	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	748	0	0
T99	7376	19	0	0
T100	5263	15	0	0
T101	2084	14	0	0
T102	14150	214	0	0
T103	9406	15	0	0
T104	2552	4	0	0
T105	4362	21	0	0
T106	1900	8	0	0
T107	3589	2	0	0
T108	15213	34	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	6385	0	0
T12	28464	0	0	0
T13	244643	0	0	0
T14	110735	0	0	0
T21	60051	0	0	0
T36	23142	0	0	0
T37	79171	0	0	0
T47	0	319	0	0
T81	384668	172	0	0
T109	0	178	0	0
T110	0	173	0	0
T111	0	229	0	0
T112	0	200	0	0
T113	0	141	0	0
T114	0	101	0	0
T115	0	212	0	0
T116	0	128	0	0
T117	47133	0	0	0
T118	72571	0	0	0
T119	240241	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	494	0	0
T99	7376	23	0	0
T100	5263	3	0	0
T101	2084	11	0	0
T102	14150	70	0	0
T103	9406	3	0	0
T104	2552	6	0	0
T105	4362	23	0	0
T106	1900	7	0	0
T120	12935	18	0	0
T121	10156	17	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	545	0	0
T99	7376	21	0	0
T101	2084	12	0	0
T102	14150	64	0	0
T103	9406	27	0	0
T104	2552	3	0	0
T105	4362	36	0	0
T106	1900	5	0	0
T107	3589	9	0	0
T120	12935	51	0	0
T121	10156	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	2004	0	0
T63	11363	0	0	0
T109	417487	0	0	0
T122	931783	22	0	0
T123	0	23	0	0
T124	0	29	0	0
T125	0	57	0	0
T126	0	11	0	0
T127	0	32	0	0
T128	0	7	0	0
T129	0	66	0	0
T130	0	20	0	0
T131	0	19	0	0
T132	184210	0	0	0
T133	223704	0	0	0
T134	35152	0	0	0
T135	52146	0	0	0
T136	72490	0	0	0
T137	112350	0	0	0
T138	187432	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	1821	0	0
T56	7763	0	0	0
T57	10912	0	0	0
T79	1652	50	0	0
T97	1678	20	0	0
T139	0	57	0	0
T140	0	61	0	0
T141	0	24	0	0
T142	0	51	0	0
T143	0	28	0	0
T144	0	56	0	0
T145	0	75	0	0
T146	0	55	0	0
T147	52735	0	0	0
T148	97501	0	0	0
T149	161820	0	0	0
T150	140824	0	0	0
T151	441080	0	0	0
T152	202207	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	595	0	0
T99	7376	20	0	0
T100	5263	12	0	0
T101	2084	10	0	0
T102	14150	69	0	0
T103	9406	8	0	0
T104	2552	11	0	0
T105	4362	41	0	0
T106	1900	10	0	0
T120	12935	26	0	0
T121	10156	11	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	664	0	0
T99	7376	17	0	0
T100	5263	23	0	0
T101	2084	7	0	0
T102	14150	87	0	0
T103	9406	15	0	0
T104	2552	9	0	0
T105	4362	35	0	0
T106	1900	15	0	0
T120	12935	17	0	0
T121	10156	19	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	468	0	0
T99	7376	5	0	0
T100	5263	13	0	0
T101	2084	6	0	0
T102	14150	42	0	0
T103	9406	6	0	0
T104	2552	15	0	0
T105	4362	16	0	0
T106	1900	6	0	0
T120	12935	18	0	0
T121	10156	5	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	667	0	0
T99	7376	45	0	0
T100	5263	12	0	0
T102	14150	74	0	0
T103	9406	19	0	0
T104	2552	16	0	0
T105	4362	15	0	0
T106	1900	12	0	0
T107	3589	46	0	0
T120	12935	23	0	0
T121	10156	12	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	512	0	0
T99	7376	27	0	0
T101	2084	18	0	0
T102	14150	113	0	0
T103	9406	5	0	0
T104	2552	18	0	0
T105	4362	30	0	0
T106	1900	10	0	0
T107	3589	23	0	0
T120	12935	15	0	0
T121	10156	4	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	519	0	0
T100	5263	32	0	0
T101	2084	1	0	0
T102	14150	80	0	0
T103	9406	11	0	0
T104	2552	5	0	0
T105	4362	30	0	0
T106	1900	6	0	0
T107	3589	28	0	0
T120	12935	17	0	0
T121	10156	16	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	563	0	0
T99	7376	12	0	0
T100	5263	4	0	0
T101	2084	24	0	0
T102	14150	66	0	0
T104	2552	4	0	0
T105	4362	17	0	0
T106	1900	11	0	0
T107	3589	38	0	0
T120	12935	21	0	0
T121	10156	20	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	514	0	0
T99	7376	20	0	0
T100	5263	6	0	0
T101	2084	15	0	0
T102	14150	30	0	0
T103	9406	20	0	0
T104	2552	19	0	0
T105	4362	21	0	0
T106	1900	11	0	0
T107	3589	24	0	0
T120	12935	34	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411862754	420	0	0
T99	7376	24	0	0
T100	5263	15	0	0
T101	2084	7	0	0
T102	14150	23	0	0
T103	9406	19	0	0
T104	2552	1	0	0
T105	4362	10	0	0
T106	1900	1	0	0
T120	12935	21	0	0
T121	10156	12	0	0