Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

158147

1

T2

74

T4

102

T6

108

ack

14133

1

T2

20

T4

15

T6

22

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	607	1			T2	1		T4	2		T9	1
high	35633	1			T2	22		T4	38		T6	29
med	64145	1			T2	35		T4	36		T6	42
sml	71196	1			T2	36		T4	40		T6	59
all_zero	699	1			T4	1		T144	2		T31	3

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86021

1

T2

56

T4

48

T6

73

auto[1]

86259

1

T2

38

T4

69

T6

57

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118188

1

T2

72

T4

90

T6

93

auto[1]

54092

1

T2

22

T4

27

T6

37

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164780

1

T2

86

T4

117

T6

122

auto[1]

7500

1

T2

8

T6

8

T9

8

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162481

1

T2

76

T4

102

T6

112

auto[1]

9799

1

T2

18

T4

15

T6

18

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163448

1

T2

77

T4

102

T6

113

auto[1]

8832

1

T2

17

T4

15

T6

17

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86021

1

T2

56

T4

48

T6

73

auto[1]

86259

1

T2

38

T4

69

T6

57

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118188

1

T2

72

T4

90

T6

93

auto[1]

54092

1

T2

22

T4

27

T6

37

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164780

1

T2

86

T4

117

T6

122

auto[1]

7500

1

T2

8

T6

8

T9

8

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162481

1

T2

76

T4

102

T6

112

auto[1]

9799

1

T2

18

T4

15

T6

18

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163448

1

T2

77

T4

102

T6

113

auto[1]

8832

1

T2

17

T4

15

T6

17

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T240

1

T241

1

T242

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T51

1

T67

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T243

1

T244

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

296

1

T9

1

T31

2

T46

6

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

136

1

T9

1

T31

1

T38

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

136

1

T6

1

T46

4

T245

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

537

1

T2

2

T6

1

T9

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

255

1

T2

1

T6

1

T31

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

250

1

T6

2

T9

1

T31

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

514

1

T2

1

T6

2

T9

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

276

1

T2

1

T31

1

T46

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

279

1

T9

1

T31

2

T38

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

11

1

T207

1

T246

1

T240

2

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T108

1

T99

1

T247

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T46

1

T108

1

T248

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50128	1			T2	28		T4	21		T6	31
write_address_byte	9799	1			T2	18		T4	15		T6	18
read_with_ack	2195	1			T28	9		T37	4		T141	15
read_with_nack	5305	1			T2	8		T6	8		T9	8
stop_byte	8832	1			T2	17		T4	15		T6	17
write_address_byte_nak	4943	1			T2	11		T6	12		T9	11
data_byte_nack	158147	1			T2	74		T4	102		T6	108
stop_byte_nack	5359	1			T2	11		T4	15		T6	13
nakok_byte_nack	79238	1			T2	30		T4	60		T6	48
nakok_addr_byte_nack	2429	1			T2	7		T6	4		T9	2