Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40297700	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10208504

1

T1

229

T2

2320

T3

233

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49623527	1			T1	10050		T2	16862		T3	195105
values[0x0]	441697	1			T1	145		T2	175		T3	70
values[0x1]	440980	1			T1	139		T2	166		T3	84

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28770473	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21735731

1

T1

4498

T2

7002

T3

48638

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	196299	1			T1	32		T2	50		T3	1
valid_sources[0x01]	246664	1			T1	49		T2	31		T3	2
valid_sources[0x02]	187560	1			T1	54		T2	84		T3	3
valid_sources[0x03]	171512	1			T1	56		T2	51		T4	18
valid_sources[0x04]	182261	1			T1	48		T2	98		T3	2
valid_sources[0x05]	175665	1			T1	38		T2	68		T3	2
valid_sources[0x06]	168526	1			T1	47		T2	22		T3	1
valid_sources[0x07]	179248	1			T1	36		T2	96		T3	4
valid_sources[0x08]	443351	1			T1	38		T2	45		T3	2
valid_sources[0x09]	175992	1			T1	31		T2	46		T4	3
valid_sources[0x0a]	202985	1			T1	38		T2	62		T3	1
valid_sources[0x0b]	178591	1			T1	46		T2	36		T3	1
valid_sources[0x0c]	173415	1			T1	51		T2	43		T3	1
valid_sources[0x0d]	174318	1			T1	41		T2	24		T3	3
valid_sources[0x0e]	193005	1			T1	36		T2	68		T3	1
valid_sources[0x0f]	177040	1			T1	37		T2	113		T3	1
valid_sources[0x10]	174122	1			T1	37		T2	184		T3	1
valid_sources[0x11]	189583	1			T1	29		T2	88		T3	1
valid_sources[0x12]	206786	1			T1	31		T2	68		T3	2
valid_sources[0x13]	174489	1			T1	35		T2	79		T3	3
valid_sources[0x14]	211196	1			T1	33		T2	40		T3	1
valid_sources[0x15]	193292	1			T1	39		T2	91		T3	1
valid_sources[0x16]	186118	1			T1	53		T2	75		T3	1
valid_sources[0x17]	181410	1			T1	42		T2	129		T3	4
valid_sources[0x18]	180745	1			T1	42		T2	100		T3	4
valid_sources[0x19]	173486	1			T1	42		T2	59		T3	3
valid_sources[0x1a]	191908	1			T1	47		T2	92		T4	17
valid_sources[0x1b]	185301	1			T1	37		T2	53		T3	1
valid_sources[0x1c]	181218	1			T1	29		T2	28		T4	19
valid_sources[0x1d]	160618	1			T1	50		T2	65		T4	7
valid_sources[0x1e]	176081	1			T1	35		T2	53		T3	2
valid_sources[0x1f]	178517	1			T1	39		T2	33		T3	1
valid_sources[0x20]	181005	1			T1	41		T2	62		T3	2
valid_sources[0x21]	175382	1			T1	40		T2	17		T3	4
valid_sources[0x22]	180091	1			T1	41		T2	76		T3	1
valid_sources[0x23]	174416	1			T1	38		T2	48		T3	1
valid_sources[0x24]	201044	1			T1	35		T2	43		T3	1
valid_sources[0x25]	287172	1			T1	30		T2	90		T3	1
valid_sources[0x26]	171462	1			T1	46		T2	38		T3	1
valid_sources[0x27]	181753	1			T1	46		T2	38		T3	3
valid_sources[0x28]	205854	1			T1	41		T2	25		T4	27
valid_sources[0x29]	190244	1			T1	32		T2	109		T3	1
valid_sources[0x2a]	187816	1			T1	29		T2	120		T4	18
valid_sources[0x2b]	174089	1			T1	43		T2	16		T3	1
valid_sources[0x2c]	193484	1			T1	31		T2	121		T3	1
valid_sources[0x2d]	171594	1			T1	39		T2	94		T3	3
valid_sources[0x2e]	188281	1			T1	35		T2	39		T4	16
valid_sources[0x2f]	205543	1			T1	41		T2	55		T3	1
valid_sources[0x30]	187387	1			T1	57		T2	49		T3	1
valid_sources[0x31]	184332	1			T1	29		T2	79		T3	1
valid_sources[0x32]	183456	1			T1	29		T2	35		T3	2
valid_sources[0x33]	175924	1			T1	39		T2	54		T3	3
valid_sources[0x34]	188991	1			T1	41		T2	98		T3	1
valid_sources[0x35]	182233	1			T1	41		T2	39		T3	1
valid_sources[0x36]	177108	1			T1	38		T2	142		T3	1
valid_sources[0x37]	182866	1			T1	36		T2	99		T4	12
valid_sources[0x38]	178484	1			T1	33		T2	60		T4	12
valid_sources[0x39]	172057	1			T1	40		T2	35		T3	1
valid_sources[0x3a]	179994	1			T1	42		T2	57		T4	15
valid_sources[0x3b]	206648	1			T1	34		T2	116		T3	2
valid_sources[0x3c]	191139	1			T1	38		T2	97		T3	2
valid_sources[0x3d]	279063	1			T1	42		T2	40		T3	2
valid_sources[0x3e]	197110	1			T1	48		T2	132		T3	3
valid_sources[0x3f]	185039	1			T1	43		T2	77		T3	2
valid_sources[0x40]	175166	1			T1	44		T2	86		T3	2
valid_sources[0x41]	177655	1			T1	59		T2	12		T3	2
valid_sources[0x42]	178993	1			T1	59		T2	35		T3	1
valid_sources[0x43]	172694	1			T1	36		T2	56		T3	3
valid_sources[0x44]	187153	1			T1	28		T2	51		T3	1
valid_sources[0x45]	180099	1			T1	42		T2	31		T4	15
valid_sources[0x46]	189360	1			T1	37		T2	59		T3	3
valid_sources[0x47]	192096	1			T1	41		T2	38		T3	2
valid_sources[0x48]	185162	1			T1	37		T2	46		T3	2
valid_sources[0x49]	173942	1			T1	42		T2	37		T3	5
valid_sources[0x4a]	178410	1			T1	22		T2	27		T3	2
valid_sources[0x4b]	173147	1			T1	31		T2	90		T3	2
valid_sources[0x4c]	188338	1			T1	37		T2	49		T3	2
valid_sources[0x4d]	170205	1			T1	26		T2	83		T4	16
valid_sources[0x4e]	178965	1			T1	32		T2	84		T3	1
valid_sources[0x4f]	179597	1			T1	49		T2	124		T3	1
valid_sources[0x50]	195700	1			T1	45		T2	54		T4	14
valid_sources[0x51]	179161	1			T1	45		T2	35		T3	1
valid_sources[0x52]	192029	1			T1	34		T2	79		T3	1
valid_sources[0x53]	185731	1			T1	52		T2	55		T4	14
valid_sources[0x54]	188623	1			T1	38		T2	48		T3	2
valid_sources[0x55]	173519	1			T1	31		T2	48		T3	1
valid_sources[0x56]	911692	1			T1	31		T2	82		T3	1
valid_sources[0x57]	182357	1			T1	49		T2	105		T4	20
valid_sources[0x58]	178755	1			T1	38		T2	118		T3	4
valid_sources[0x59]	174897	1			T1	45		T2	63		T4	11
valid_sources[0x5a]	200135	1			T1	40		T2	9		T3	2
valid_sources[0x5b]	179237	1			T1	38		T2	56		T3	2
valid_sources[0x5c]	188606	1			T1	40		T2	47		T3	2
valid_sources[0x5d]	193310	1			T1	57		T2	48		T3	1
valid_sources[0x5e]	171003	1			T1	44		T2	70		T3	1
valid_sources[0x5f]	178184	1			T1	45		T2	41		T3	1
valid_sources[0x60]	175741	1			T1	51		T2	103		T3	2
valid_sources[0x61]	177187	1			T1	45		T2	105		T3	1
valid_sources[0x62]	189901	1			T1	52		T2	41		T3	2
valid_sources[0x63]	369111	1			T1	48		T2	51		T4	9
valid_sources[0x64]	175414	1			T1	41		T2	113		T3	3
valid_sources[0x65]	183048	1			T1	38		T2	32		T3	1
valid_sources[0x66]	168159	1			T1	51		T2	61		T4	8
valid_sources[0x67]	184388	1			T1	56		T2	43		T3	2
valid_sources[0x68]	183406	1			T1	33		T2	39		T3	1
valid_sources[0x69]	180270	1			T1	41		T2	59		T3	1
valid_sources[0x6a]	179890	1			T1	45		T2	72		T3	2
valid_sources[0x6b]	189987	1			T1	38		T2	33		T3	2
valid_sources[0x6c]	186143	1			T1	47		T2	58		T3	1
valid_sources[0x6d]	182709	1			T1	37		T2	101		T3	4
valid_sources[0x6e]	172492	1			T1	29		T2	49		T3	4
valid_sources[0x6f]	182903	1			T1	38		T2	63		T3	1
valid_sources[0x70]	178661	1			T1	32		T2	70		T4	8
valid_sources[0x71]	185332	1			T1	27		T2	152		T3	1
valid_sources[0x72]	174399	1			T1	50		T2	56		T3	4
valid_sources[0x73]	168649	1			T1	56		T2	54		T3	2
valid_sources[0x74]	183413	1			T1	38		T2	54		T3	2
valid_sources[0x75]	183135	1			T1	45		T2	29		T3	3
valid_sources[0x76]	184914	1			T1	51		T2	42		T3	3
valid_sources[0x77]	173839	1			T1	28		T2	64		T3	1
valid_sources[0x78]	178395	1			T1	45		T2	1		T4	6
valid_sources[0x79]	182003	1			T1	44		T2	74		T3	1
valid_sources[0x7a]	198774	1			T1	54		T2	33		T3	2
valid_sources[0x7b]	174163	1			T1	37		T2	40		T4	22
valid_sources[0x7c]	214674	1			T1	43		T2	11		T3	1
valid_sources[0x7d]	171314	1			T1	36		T2	70		T3	1
valid_sources[0x7e]	196517	1			T1	41		T2	145		T4	9
valid_sources[0x7f]	189752	1			T1	44		T2	36		T3	1
valid_sources[0x80]	193997	1			T1	31		T2	111		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9815404

1

T1

129

T2

2102

T3

180

values[0x0]

all_enables

biggest_size

229920

1

T1

60

T2

125

T3

35

values[0x1]

all_enables

biggest_size

163180

1

T1

40

T2

93

T3

18