Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	390532734	0	0	0
ctrl_rd_A	390532734	1508	0	0
host_fifo_config_rd_A	390532734	5488	0	0
host_nack_handler_timeout_rd_A	390532734	1263	0	0
host_timeout_ctrl_rd_A	390532734	1080	0	0
intr_enable_rd_A	390532734	2791	0	0
ovrd_rd_A	390532734	2268	0	0
target_fifo_config_rd_A	390532734	1184	0	0
target_id_rd_A	390532734	1311	0	0
target_timeout_ctrl_rd_A	390532734	1212	0	0
timeout_ctrl_rd_A	390532734	1264	0	0
timing0_rd_A	390532734	1111	0	0
timing1_rd_A	390532734	1321	0	0
timing2_rd_A	390532734	1199	0	0
timing3_rd_A	390532734	1193	0	0
timing4_rd_A	390532734	1338	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1508	0	0
T88	13865	162	0	0
T89	2134	32	0	0
T90	5563	50	0	0
T91	1162	15	0	0
T92	3368	16	0	0
T93	2012	9	0	0
T94	2757	13	0	0
T95	6000	13	0	0
T96	5192	20	0	0
T97	4696	13	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	5488	0	0
T42	883063	227	0	0
T48	0	200	0	0
T51	280048	126	0	0
T62	109498	0	0	0
T98	0	76	0	0
T99	0	158	0	0
T100	0	160	0	0
T101	0	124	0	0
T102	0	60	0	0
T103	0	359	0	0
T104	0	94	0	0
T105	60825	0	0	0
T106	31653	0	0	0
T107	213358	0	0	0
T108	454902	0	0	0
T109	212057	0	0	0
T110	229032	0	0	0
T111	405728	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1263	0	0
T88	13865	50	0	0
T89	2134	5	0	0
T90	5563	40	0	0
T91	1162	4	0	0
T92	3368	23	0	0
T93	2012	5	0	0
T94	2757	10	0	0
T95	6000	3	0	0
T96	5192	25	0	0
T97	4696	6	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1080	0	0
T88	13865	39	0	0
T89	2134	7	0	0
T90	5563	22	0	0
T91	1162	7	0	0
T92	3368	15	0	0
T93	2012	7	0	0
T94	2757	13	0	0
T95	6000	24	0	0
T96	5192	14	0	0
T97	4696	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	2791	0	0
T48	0	14	0	0
T88	0	425	0	0
T89	0	96	0	0
T90	0	40	0	0
T91	0	5	0	0
T99	145613	19	0	0
T112	0	36	0	0
T113	0	14	0	0
T114	0	8	0	0
T115	0	24	0	0
T116	74722	0	0	0
T117	102063	0	0	0
T118	64301	0	0	0
T119	1703	0	0	0
T120	44346	0	0	0
T121	22266	0	0	0
T122	68853	0	0	0
T123	117767	0	0	0
T124	90049	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	2268	0	0
T18	40000	0	0	0
T34	11965	0	0	0
T72	166924	0	0	0
T83	1038	21	0	0
T86	973003	0	0	0
T87	115776	0	0	0
T125	0	26	0	0
T126	0	39	0	0
T127	0	85	0	0
T128	0	30	0	0
T129	0	70	0	0
T130	0	45	0	0
T131	0	31	0	0
T132	0	29	0	0
T133	0	64	0	0
T134	142588	0	0	0
T135	77347	0	0	0
T136	38652	0	0	0
T137	101046	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1184	0	0
T88	13865	63	0	0
T89	2134	11	0	0
T90	5563	23	0	0
T91	1162	7	0	0
T92	3368	22	0	0
T93	2012	3	0	0
T94	2757	14	0	0
T95	6000	17	0	0
T96	5192	14	0	0
T97	4696	4	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1311	0	0
T88	13865	96	0	0
T89	2134	38	0	0
T90	5563	23	0	0
T91	1162	1	0	0
T92	3368	24	0	0
T93	2012	7	0	0
T94	2757	1	0	0
T96	5192	8	0	0
T97	4696	2	0	0
T138	2818	9	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1212	0	0
T88	13865	60	0	0
T89	2134	14	0	0
T90	5563	62	0	0
T91	1162	8	0	0
T92	3368	33	0	0
T93	2012	9	0	0
T94	2757	17	0	0
T95	6000	11	0	0
T96	5192	10	0	0
T97	4696	5	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1264	0	0
T88	13865	70	0	0
T89	2134	18	0	0
T90	5563	33	0	0
T91	1162	17	0	0
T92	3368	21	0	0
T93	2012	6	0	0
T94	2757	3	0	0
T95	6000	10	0	0
T97	4696	1	0	0
T138	2818	2	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1111	0	0
T88	13865	52	0	0
T89	2134	7	0	0
T90	5563	33	0	0
T91	1162	4	0	0
T92	3368	25	0	0
T93	2012	2	0	0
T94	2757	11	0	0
T95	6000	21	0	0
T96	5192	20	0	0
T97	4696	3	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1321	0	0
T88	13865	56	0	0
T89	2134	8	0	0
T90	5563	62	0	0
T91	1162	13	0	0
T92	3368	28	0	0
T93	2012	13	0	0
T94	2757	23	0	0
T95	6000	31	0	0
T96	5192	17	0	0
T97	4696	15	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1199	0	0
T88	13865	96	0	0
T89	2134	11	0	0
T90	5563	29	0	0
T92	3368	33	0	0
T93	2012	7	0	0
T94	2757	1	0	0
T95	6000	7	0	0
T96	5192	5	0	0
T97	4696	13	0	0
T138	2818	2	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1193	0	0
T88	13865	41	0	0
T89	2134	13	0	0
T90	5563	99	0	0
T91	1162	8	0	0
T92	3368	17	0	0
T93	2012	13	0	0
T94	2757	11	0	0
T96	5192	17	0	0
T97	4696	3	0	0
T138	2818	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390532734	1338	0	0
T88	13865	62	0	0
T89	2134	9	0	0
T90	5563	49	0	0
T91	1162	6	0	0
T92	3368	38	0	0
T93	2012	10	0	0
T94	2757	5	0	0
T95	6000	9	0	0
T96	5192	5	0	0
T97	4696	9	0	0