Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

166290

1

T4

260

T8

3

T9

1006

ack

15467

1

T4

5

T8

2

T9

148

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	663	1			T9	5		T43	3		T40	7
high	37216	1			T4	47		T9	234		T10	32
med	67415	1			T4	115		T9	406		T10	50
sml	75733	1			T4	101		T8	4		T9	507
all_zero	730	1			T4	2		T8	1		T9	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90706

1

T4

135

T8

2

T9

568

auto[1]

91051

1

T4

130

T8

3

T9

586

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124815

1

T4

188

T8

2

T9

822

auto[1]

56942

1

T4

77

T8

3

T9

332

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173578

1

T4

264

T8

1

T9

1079

auto[1]

8179

1

T4

1

T8

4

T9

75

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171212

1

T4

261

T8

4

T9

1058

auto[1]

10545

1

T4

4

T8

1

T9

96

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172148

1

T4

263

T8

4

T9

1065

auto[1]

9609

1

T4

2

T8

1

T9

89

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90706

1

T4

135

T8

2

T9

568

auto[1]

91051

1

T4

130

T8

3

T9

586

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124815

1

T4

188

T8

2

T9

822

auto[1]

56942

1

T4

77

T8

3

T9

332

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173578

1

T4

264

T8

1

T9

1079

auto[1]

8179

1

T4

1

T8

4

T9

75

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171212

1

T4

261

T8

4

T9

1058

auto[1]

10545

1

T4

4

T8

1

T9

96

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172148

1

T4

263

T8

4

T9

1065

auto[1]

9609

1

T4

2

T8

1

T9

89

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T49

1

T235

1

T236

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T237

1

T238

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T239

1

T240

1

T241

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

330

1

T9

2

T10

2

T63

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

168

1

T40

1

T41

1

T42

11

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

151

1

T9

1

T63

1

T40

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

541

1

T9

5

T43

2

T63

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

280

1

T9

4

T43

1

T40

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

297

1

T10

1

T43

1

T44

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

567

1

T9

5

T10

1

T63

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

296

1

T9

3

T44

1

T40

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

275

1

T9

1

T43

3

T40

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T242

1

T243

1

T244

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T245

1

T246

1

T240

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T247

1

T248

1

T123

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	52989	1			T4	92		T9	309		T10	37
write_address_byte	10545	1			T4	4		T8	1		T9	96
read_with_ack	2347	1			T8	3		T9	14		T43	2
read_with_nack	5832	1			T4	1		T8	1		T9	61
stop_byte	9609	1			T4	2		T8	1		T9	89
write_address_byte_nak	5309	1			T9	41		T10	11		T43	10
data_byte_nack	166290	1			T4	260		T8	3		T9	1006
stop_byte_nack	5725	1			T4	1		T8	1		T9	38
nakok_byte_nack	83261	1			T4	127		T8	2		T9	519
nakok_addr_byte_nack	2636	1			T9	20		T10	5		T43	4