Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
91.30 91.30 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov_cg 91.30 1 100 1 64 64



Group Instance : i2c_protocol_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.30 1 100 1 64 64



Summary for Group Instance i2c_protocol_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 47 5 42 89.36
Crosses 68 5 63 92.65


Variables for Group Instance i2c_protocol_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
RStart_before_read_data_ACK_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_Ack_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_transmission_cp 1 0 1 100.00 100 1 1 0
RStart_during_read_data_cp 1 0 1 100.00 100 1 1 0
RStart_during_rw_bit_cp 1 1 0 0.00 100 1 1 0
RStart_during_write_data_cp 1 0 1 100.00 100 1 1 0
Read_data_ack_before_stop_cp 1 1 0 0.00 100 1 1 0
Rstart_after_Address_Ack_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Nack_cp 1 0 1 100.00 100 1 1 0
Start_followed_by_Rstart_cp 1 0 1 100.00 100 1 1 2
Stop_after_read_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_read_data_ack_cp 1 1 0 0.00 100 1 1 0
Stop_after_write_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_addr_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_data_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_read_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_write_cp 1 1 0 0.00 100 1 1 0
bus_state_cp 17 0 17 100.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0
num_rd_bytes_cp 5 0 5 100.00 100 1 1 0
num_wr_bytes_cp 5 0 5 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
bus_state_x_ip_mode_cp 34 1 33 97.06 100 1 1 0
num_rd_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
num_wr_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
Stop_after_write_data_ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Stop_after_read_data_ack_x_ip_mode_cp 2 2 0 0.00 100 1 1 0
Stop_after_write_data_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_read_data_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Start_followed_by_Rstart_cp_x_ip_mode_cp 2 1 1 50.00 100 1 1 0


Summary for Variable RStart_before_read_data_ACK_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_before_read_data_ACK_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_before_read_data_ACK_Nack 20428 1 T1 16 T2 24 T5 20


Summary for Variable RStart_during_address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_address_Acknowledge 8 1 T15 4 T16 4


Summary for Variable RStart_during_address_transmission_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_transmission_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_address_transmission 9 1 T25 1 T12 1 T26 1


Summary for Variable RStart_during_read_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_read_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_read_data 24 1 T15 12 T16 12


Summary for Variable RStart_during_rw_bit_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_rw_bit 0 1 1


Summary for Variable RStart_during_write_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_write_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_write_data 17916 1 T2 18 T3 26 T5 19


Summary for Variable Read_data_ack_before_stop_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Read_data_ack_before_stop_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Read_data_ack_before_stop 0 1 1


Summary for Variable Rstart_after_Address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack 31 1 T220 1 T15 10 T221 1


Summary for Variable Rstart_after_Address_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack 62 1 T44 3 T45 3 T46 2


Summary for Variable Start_followed_by_Rstart_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[1] 2 1 T222 2


Summary for Variable Stop_after_read_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack 16483 1 T1 2 T2 9 T4 1


Summary for Variable Stop_after_read_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_after_read_data_ack_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_after_read_data_ack 0 1 1


Summary for Variable Stop_after_write_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack 49 1 T44 3 T45 2 T135 2


Summary for Variable Stop_after_write_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack 8372 1 T2 6 T4 1 T5 7


Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_addr_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_addr 12 1 T27 1 T13 1 T28 1


Summary for Variable Stop_without_ACK_after_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_data 4412 1 T2 6 T5 7 T6 6


Summary for Variable Stop_without_ACK_after_read_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_read 0 1 1


Summary for Variable Stop_without_ACK_after_write_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_write_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_write 0 1 1


Summary for Variable bus_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 17 0 17 100.00


User Defined Bins for bus_state_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle 217430 1 T1 1 T2 1 T3 1
stop 26050 1 T1 2 T2 15 T4 2
write_data_nack 28608 1 T44 1468 T45 2154 T46 27
write_data_ack 1203597 1 T2 1069 T3 906 T4 909
read_data_nack 134896 1 T1 60 T2 108 T4 8
read_data_ack 1943591 1 T1 432 T2 781 T4 200
write_data 8097899 1 T2 7743 T3 6456 T4 5490
read_data 13736201 1 T1 2990 T2 5418 T4 1453
write_addr_nack 23096 1 T44 905 T45 1509 T46 990
write_addr_ack 93219 1 T2 87 T3 91 T4 12
read_addr_nack 82170 1 T44 900 T45 1378 T46 1918
read_addr_ack 132281 1 T1 67 T2 116 T4 7
write 110080 1 T2 100 T3 108 T4 12
read 113887 1 T1 57 T2 99 T4 6
addr 1350978 1 T1 392 T2 1061 T3 631
rstart 100674 1 T1 40 T2 104 T3 78
start 68807 1 T1 7 T2 38 T3 3


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 12116202 1 T1 4048 T2 16740 T3 8274
host 15347262 1 T4 8208 T8 7702 T9 151320


Summary for Variable num_rd_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_rd_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 56239 1 T8 22 T9 1173 T43 98
high 2052401 1 T8 554 T9 26111 T43 3293
mid 3114432 1 T1 200 T2 227 T4 414
low 7667373 1 T1 2451 T2 4635 T4 1140
one 859942 1 T1 441 T2 761 T4 56


Summary for Variable num_wr_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_wr_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 20528 1 T4 24 T9 164 T43 174
high 958995 1 T4 496 T9 3422 T43 3418
mid 1401482 1 T2 744 T3 178 T4 538
low 5120172 1 T2 6731 T3 5825 T4 518
one 678232 1 T2 718 T3 706 T4 50


Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 34 1 33 97.06 1


Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Uncovered bins
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[read_addr_nack] [device] 0 1 1


Covered bins
bus_state_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle device 213785 1 T1 1 T2 1 T3 1
idle host 3645 1 T4 1 T8 1 T9 1
stop device 10707 1 T1 2 T2 15 T5 14
stop host 15343 1 T4 2 T8 1 T9 144
write_data_nack device 12 1 T15 6 T16 6 - -
write_data_nack host 28596 1 T44 1468 T45 2154 T46 27
write_data_ack device 628708 1 T2 1069 T3 906 T5 714
write_data_ack host 574889 1 T4 909 T8 12 T9 3533
read_data_nack device 86264 1 T1 60 T2 108 T5 88
read_data_nack host 48632 1 T4 8 T8 4 T9 456
read_data_ack device 639199 1 T1 432 T2 781 T5 614
read_data_ack host 1304392 1 T4 200 T8 950 T9 14954
write_data device 4652415 1 T2 7743 T3 6456 T5 5146
write_data host 3445484 1 T4 5490 T8 67 T9 21189
read_data device 4348698 1 T1 2990 T2 5418 T5 4234
read_data host 9387503 1 T4 1453 T8 6613 T9 107088
write_addr_nack device 8 1 T15 4 T16 4 - -
write_addr_nack host 23088 1 T44 905 T45 1509 T46 990
write_addr_ack device 76978 1 T2 87 T3 91 T5 92
write_addr_ack host 16241 1 T4 12 T8 4 T9 125
read_addr_nack host 82170 1 T44 900 T45 1378 T46 1918
read_addr_ack device 93478 1 T1 67 T2 116 T5 91
read_addr_ack host 38803 1 T4 7 T8 4 T9 398
write device 90726 1 T2 100 T3 108 T5 108
write host 19354 1 T4 12 T8 4 T9 136
read device 80109 1 T1 57 T2 99 T5 81
read host 33778 1 T4 6 T8 3 T9 342
addr device 1066791 1 T1 392 T2 1061 T3 631
addr host 284187 1 T4 94 T8 35 T9 2577
rstart device 99571 1 T1 40 T2 104 T3 78
rstart host 1103 1 T4 6 T9 7 T43 4
start device 28753 1 T1 7 T2 38 T3 3
start host 40054 1 T4 8 T8 4 T9 370


Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_rd_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 26 1 T223 26 - - - -
device high 7041 1 T27 99 T224 224 T225 3
device mid 219404 1 T1 200 T2 227 T5 29
device low 3715356 1 T1 2451 T2 4635 T5 3703
device one 577799 1 T1 441 T2 761 T5 632
host sixtyfour 56213 1 T8 22 T9 1173 T43 98
host high 2045360 1 T8 554 T9 26111 T43 3293
host mid 2895028 1 T4 414 T8 598 T9 34622
host low 3952017 1 T4 1140 T8 552 T9 43110
host one 282143 1 T4 56 T8 26 T9 2961


Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_wr_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 462 1 T226 28 T227 28 T228 30
device high 19909 1 T19 376 T115 135 T138 90
device mid 280983 1 T2 744 T3 178 T5 408
device low 3811742 1 T2 6731 T3 5825 T5 4124
device one 566058 1 T2 718 T3 706 T5 668
host sixtyfour 20066 1 T4 24 T9 164 T43 174
host high 939086 1 T4 496 T9 3422 T43 3418
host mid 1120499 1 T4 538 T9 4674 T10 409
host low 1308430 1 T4 518 T8 33 T9 6544
host one 112174 1 T4 50 T8 24 T9 709


Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins
Stop_after_write_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack device 4404 1 T2 6 T5 7 T6 6
Stop_after_write_data_ack host 3968 1 T4 1 T9 31 T10 10


Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 2 0 0.00 2


Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Uncovered bins
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 2


Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Element holes
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Covered bins
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack host 49 1 T44 3 T45 2 T135 2


Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins
Stop_after_read_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack device 5903 1 T1 2 T2 9 T5 7
Stop_after_read_data_Nack host 10580 1 T4 1 T8 1 T9 113


Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Bins
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack device 20 1 T15 10 T16 10 - -
Rstart_after_Address_Ack host 11 1 T220 1 T221 1 T229 1


Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Bins
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack device 8 1 T15 4 T16 4 - -
Rstart_after_Address_Nack host 54 1 T44 3 T45 3 T46 2


Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Element holes
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Excluded/Illegal bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTSTATUS
[auto[0]] [device , host] -- Excluded (2 bins)


Covered bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNT
auto[1] host 2 1 T222 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%