Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39561297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9908638

1

T1

75

T2

368

T3

175

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48545022	1			T1	196		T2	1034		T3	322
values[0x0]	462606	1			T1	89		T2	219		T3	21
values[0x1]	462307	1			T1	89		T2	188		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28213383	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21256552

1

T1

145

T2

686

T3

215

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	185144	1			T1	1		T2	4		T4	206
valid_sources[0x01]	176750	1			T2	6		T3	1		T4	219
valid_sources[0x02]	235838	1			T1	1		T2	7		T3	1
valid_sources[0x03]	180133	1			T1	1		T2	5		T4	228
valid_sources[0x04]	179497	1			T1	3		T2	9		T4	245
valid_sources[0x05]	312194	1			T1	1		T2	6		T3	1
valid_sources[0x06]	180930	1			T1	2		T4	223		T7	1
valid_sources[0x07]	178766	1			T1	1		T2	2		T4	215
valid_sources[0x08]	177340	1			T1	3		T2	4		T3	6
valid_sources[0x09]	169247	1			T1	6		T2	3		T4	198
valid_sources[0x0a]	248368	1			T1	3		T2	7		T4	216
valid_sources[0x0b]	191866	1			T1	2		T2	7		T4	206
valid_sources[0x0c]	182696	1			T1	2		T2	3		T4	222
valid_sources[0x0d]	178144	1			T1	2		T2	1		T3	1
valid_sources[0x0e]	185233	1			T2	2		T3	3		T4	222
valid_sources[0x0f]	172385	1			T3	1		T4	229		T8	2401
valid_sources[0x10]	182495	1			T1	1		T2	6		T3	3
valid_sources[0x11]	194728	1			T2	8		T3	12		T4	219
valid_sources[0x12]	183858	1			T1	1		T2	4		T3	9
valid_sources[0x13]	186056	1			T2	8		T3	2		T4	219
valid_sources[0x14]	165582	1			T2	3		T4	203		T8	2491
valid_sources[0x15]	255336	1			T1	6		T2	5		T3	3
valid_sources[0x16]	186153	1			T2	10		T3	3		T4	202
valid_sources[0x17]	271358	1			T2	2		T4	200		T8	2507
valid_sources[0x18]	347834	1			T1	1		T2	7		T3	6
valid_sources[0x19]	196416	1			T2	7		T4	238		T8	2347
valid_sources[0x1a]	175340	1			T1	1		T2	2		T3	3
valid_sources[0x1b]	176945	1			T1	6		T2	5		T3	1
valid_sources[0x1c]	182802	1			T1	2		T2	8		T4	176
valid_sources[0x1d]	173250	1			T1	3		T2	5		T3	3
valid_sources[0x1e]	187047	1			T2	5		T4	197		T8	2432
valid_sources[0x1f]	185120	1			T2	14		T4	243		T8	2467
valid_sources[0x20]	192139	1			T1	3		T2	5		T4	232
valid_sources[0x21]	192829	1			T1	1		T2	6		T3	4
valid_sources[0x22]	175320	1			T1	3		T2	6		T3	1
valid_sources[0x23]	181244	1			T1	2		T2	5		T3	2
valid_sources[0x24]	186383	1			T1	1		T2	8		T4	221
valid_sources[0x25]	174500	1			T1	2		T2	5		T4	194
valid_sources[0x26]	194084	1			T1	3		T2	5		T3	5
valid_sources[0x27]	172353	1			T1	2		T2	5		T3	10
valid_sources[0x28]	186204	1			T1	4		T2	2		T4	201
valid_sources[0x29]	200000	1			T2	5		T3	3		T4	207
valid_sources[0x2a]	172327	1			T2	7		T4	210		T8	2465
valid_sources[0x2b]	167592	1			T1	2		T2	9		T3	6
valid_sources[0x2c]	224539	1			T1	1		T2	8		T4	219
valid_sources[0x2d]	186153	1			T1	1		T2	4		T4	220
valid_sources[0x2e]	176202	1			T1	1		T2	7		T4	223
valid_sources[0x2f]	174331	1			T1	1		T2	7		T4	218
valid_sources[0x30]	207556	1			T1	2		T2	5		T4	245
valid_sources[0x31]	185563	1			T1	1		T2	9		T3	3
valid_sources[0x32]	274342	1			T1	1		T2	5		T3	1
valid_sources[0x33]	175880	1			T2	6		T4	185		T8	2432
valid_sources[0x34]	179505	1			T2	9		T3	1		T4	211
valid_sources[0x35]	177936	1			T2	5		T4	201		T6	457
valid_sources[0x36]	198107	1			T1	4		T2	6		T4	225
valid_sources[0x37]	185644	1			T1	1		T2	8		T3	3
valid_sources[0x38]	167837	1			T2	10		T4	242		T8	2452
valid_sources[0x39]	170012	1			T1	1		T2	7		T3	2
valid_sources[0x3a]	171792	1			T1	1		T2	6		T4	251
valid_sources[0x3b]	179146	1			T1	3		T2	7		T4	218
valid_sources[0x3c]	186319	1			T2	15		T3	2		T4	211
valid_sources[0x3d]	273505	1			T1	2		T2	1		T4	218
valid_sources[0x3e]	180943	1			T2	2		T3	4		T4	214
valid_sources[0x3f]	204029	1			T2	1		T4	240		T8	2354
valid_sources[0x40]	180678	1			T1	1		T2	3		T3	3
valid_sources[0x41]	169816	1			T2	2		T3	7		T4	209
valid_sources[0x42]	171348	1			T1	1		T2	11		T3	3
valid_sources[0x43]	184147	1			T1	3		T2	7		T3	1
valid_sources[0x44]	181463	1			T1	2		T2	3		T3	1
valid_sources[0x45]	183963	1			T1	3		T2	6		T3	1
valid_sources[0x46]	180056	1			T1	3		T2	6		T4	214
valid_sources[0x47]	167843	1			T1	1		T2	4		T3	1
valid_sources[0x48]	169630	1			T1	1		T2	7		T3	1
valid_sources[0x49]	213079	1			T1	1		T2	12		T3	5
valid_sources[0x4a]	180820	1			T2	6		T3	1		T4	218
valid_sources[0x4b]	184280	1			T1	3		T2	11		T4	204
valid_sources[0x4c]	221165	1			T2	10		T3	5		T4	205
valid_sources[0x4d]	175544	1			T2	11		T4	236		T8	2386
valid_sources[0x4e]	175903	1			T1	6		T2	5		T3	2
valid_sources[0x4f]	212136	1			T1	4		T2	3		T3	4
valid_sources[0x50]	204300	1			T1	2		T2	4		T4	224
valid_sources[0x51]	186053	1			T1	1		T2	7		T3	1
valid_sources[0x52]	178839	1			T1	2		T2	6		T3	3
valid_sources[0x53]	180124	1			T1	4		T2	3		T3	2
valid_sources[0x54]	195097	1			T1	1		T2	6		T4	222
valid_sources[0x55]	185984	1			T1	2		T3	2		T4	218
valid_sources[0x56]	191774	1			T1	2		T2	2		T3	1
valid_sources[0x57]	167208	1			T1	1		T2	6		T3	3
valid_sources[0x58]	179462	1			T1	1		T2	5		T3	1
valid_sources[0x59]	174231	1			T1	2		T2	8		T3	1
valid_sources[0x5a]	181233	1			T1	2		T2	8		T3	6
valid_sources[0x5b]	186379	1			T1	1		T2	14		T4	192
valid_sources[0x5c]	169137	1			T1	2		T2	4		T4	213
valid_sources[0x5d]	165924	1			T1	2		T2	7		T3	6
valid_sources[0x5e]	400662	1			T2	3		T4	233		T8	2408
valid_sources[0x5f]	185890	1			T1	1		T2	10		T4	214
valid_sources[0x60]	198371	1			T1	2		T2	3		T3	1
valid_sources[0x61]	178517	1			T2	6		T4	176		T8	2557
valid_sources[0x62]	174085	1			T1	3		T2	12		T4	209
valid_sources[0x63]	182637	1			T2	4		T4	230		T8	2393
valid_sources[0x64]	181509	1			T1	3		T2	7		T3	6
valid_sources[0x65]	193315	1			T1	3		T2	9		T4	213
valid_sources[0x66]	182589	1			T2	7		T3	1		T4	230
valid_sources[0x67]	171715	1			T2	4		T4	205		T8	2451
valid_sources[0x68]	179909	1			T2	4		T3	2		T4	207
valid_sources[0x69]	185105	1			T1	2		T2	3		T3	1
valid_sources[0x6a]	177044	1			T1	5		T2	5		T3	2
valid_sources[0x6b]	182547	1			T1	3		T2	5		T3	2
valid_sources[0x6c]	182591	1			T1	4		T2	5		T3	1
valid_sources[0x6d]	167549	1			T1	1		T2	3		T3	1
valid_sources[0x6e]	169728	1			T1	1		T2	7		T4	230
valid_sources[0x6f]	201849	1			T1	1		T2	8		T3	3
valid_sources[0x70]	174803	1			T1	2		T2	4		T3	1
valid_sources[0x71]	165027	1			T1	1		T2	4		T4	219
valid_sources[0x72]	171596	1			T1	2		T2	6		T3	4
valid_sources[0x73]	194297	1			T2	5		T3	1		T4	221
valid_sources[0x74]	203257	1			T2	5		T4	208		T8	2475
valid_sources[0x75]	172352	1			T1	2		T2	7		T3	1
valid_sources[0x76]	194614	1			T1	1		T2	5		T3	1
valid_sources[0x77]	177953	1			T2	8		T4	216		T6	874
valid_sources[0x78]	181121	1			T2	5		T3	1		T4	239
valid_sources[0x79]	264263	1			T1	3		T2	6		T3	2
valid_sources[0x7a]	175589	1			T1	2		T2	16		T3	1
valid_sources[0x7b]	294560	1			T1	1		T2	6		T3	3
valid_sources[0x7c]	176472	1			T1	2		T2	2		T4	218
valid_sources[0x7d]	193803	1			T1	1		T2	4		T3	2
valid_sources[0x7e]	176572	1			T1	1		T2	1		T4	237
valid_sources[0x7f]	185455	1			T1	2		T2	4		T4	206
valid_sources[0x80]	169069	1			T1	1		T2	5		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9492646

1

T1

14

T2

225

T3

151

values[0x0]

all_enables

biggest_size

242784

1

T1

39

T2

94

T3

14

values[0x1]

all_enables

biggest_size

173208

1

T1

22

T2

49

T3

10