Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64
i2c_env_pkg.b2b_txn_target_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	3757	1			T4	1		T9	34		T10	12
b2b_read_same_addr	257	1			T4	2		T9	4		T43	1
write_after_read_different_addr	3604	1			T4	1		T9	34		T10	3
write_after_read_same_addr	62	1			T35	1		T41	2		T49	1
read_after_write_different_addr	3587	1			T8	1		T9	34		T10	3
read_after_write_same_addr	70	1			T51	1		T40	1		T41	1
b2b_write_different_addr	3550	1			T9	38		T10	1		T43	2
b2b_write_same_addr	275	1			T9	3		T43	1		T44	2

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	316	1			T34	15		T81	10		T254	1
b2b_read_same_addr	444	1			T34	7		T81	10		T82	5
write_after_read_different_addr	12877	1			T2	33		T5	27		T6	6
write_after_read_same_addr	208	1			T255	32		T256	16		T257	5
read_after_write_different_addr	12868	1			T2	33		T5	27		T6	6
read_after_write_same_addr	214	1			T255	32		T256	16		T257	5
b2b_write_different_addr	23514	1			T1	37		T6	36		T20	54
b2b_write_same_addr	213207	1			T1	3		T2	354		T3	289