Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	406198472	0	0	0
ctrl_rd_A	406198472	2206	0	0
host_fifo_config_rd_A	406198472	6056	0	0
host_nack_handler_timeout_rd_A	406198472	1224	0	0
host_timeout_ctrl_rd_A	406198472	896	0	0
intr_enable_rd_A	406198472	4624	0	0
ovrd_rd_A	406198472	2016	0	0
target_fifo_config_rd_A	406198472	1221	0	0
target_id_rd_A	406198472	1675	0	0
target_timeout_ctrl_rd_A	406198472	1197	0	0
timeout_ctrl_rd_A	406198472	1488	0	0
timing0_rd_A	406198472	1167	0	0
timing1_rd_A	406198472	1132	0	0
timing2_rd_A	406198472	1085	0	0
timing3_rd_A	406198472	1065	0	0
timing4_rd_A	406198472	1267	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	2206	0	0
T97	3416	32	0	0
T98	14527	223	0	0
T99	10835	34	0	0
T100	7345	27	0	0
T101	13273	211	0	0
T102	7155	10	0	0
T103	2837	42	0	0
T104	11233	21	0	0
T105	2214	46	0	0
T106	3760	45	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	6056	0	0
T39	138434	0	0	0
T41	104435	60	0	0
T42	224537	590	0	0
T49	0	85	0	0
T53	8336	0	0	0
T68	122304	0	0	0
T107	0	68	0	0
T108	0	94	0	0
T109	0	200	0	0
T110	0	111	0	0
T111	0	222	0	0
T112	0	135	0	0
T113	0	115	0	0
T114	70272	0	0	0
T115	553417	0	0	0
T116	71391	0	0	0
T117	334032	0	0	0
T118	456991	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1224	0	0
T97	3416	23	0	0
T98	14527	82	0	0
T99	10835	12	0	0
T100	7345	24	0	0
T101	13273	83	0	0
T102	7155	9	0	0
T103	2837	23	0	0
T104	11233	45	0	0
T105	2214	20	0	0
T119	1880	5	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	896	0	0
T97	3416	12	0	0
T98	14527	67	0	0
T99	10835	29	0	0
T100	7345	7	0	0
T101	13273	20	0	0
T102	7155	13	0	0
T103	2837	10	0	0
T104	11233	52	0	0
T105	2214	13	0	0
T119	1880	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	4624	0	0
T39	138434	0	0	0
T41	104435	5	0	0
T42	224537	14	0	0
T48	0	4	0	0
T49	0	17	0	0
T53	8336	0	0	0
T57	0	16	0	0
T68	122304	0	0	0
T112	0	15	0	0
T114	70272	0	0	0
T115	553417	0	0	0
T116	71391	0	0	0
T117	334032	0	0	0
T118	456991	0	0	0
T120	0	84	0	0
T121	0	30	0	0
T122	0	17	0	0
T123	0	4	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	2016	0	0
T36	133680	0	0	0
T69	115293	0	0	0
T95	2252	47	0	0
T124	0	55	0	0
T125	0	46	0	0
T126	0	17	0	0
T127	0	33	0	0
T128	0	39	0	0
T129	0	27	0	0
T130	0	65	0	0
T131	0	19	0	0
T132	0	37	0	0
T133	12898	0	0	0
T134	20147	0	0	0
T135	61721	0	0	0
T136	255738	0	0	0
T137	160750	0	0	0
T138	100101	0	0	0
T139	107753	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1221	0	0
T97	3416	2	0	0
T98	14527	118	0	0
T99	10835	46	0	0
T100	7345	27	0	0
T101	13273	68	0	0
T102	7155	16	0	0
T103	2837	22	0	0
T104	11233	26	0	0
T105	2214	10	0	0
T106	3760	3	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1675	0	0
T97	3416	36	0	0
T98	14527	219	0	0
T99	10835	33	0	0
T100	7345	22	0	0
T101	13273	107	0	0
T102	7155	14	0	0
T103	2837	31	0	0
T104	11233	25	0	0
T105	2214	26	0	0
T119	1880	8	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1197	0	0
T97	3416	5	0	0
T98	14527	113	0	0
T99	10835	32	0	0
T100	7345	18	0	0
T101	13273	50	0	0
T102	7155	4	0	0
T103	2837	18	0	0
T104	11233	40	0	0
T105	2214	8	0	0
T119	1880	5	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1488	0	0
T97	3416	14	0	0
T98	14527	199	0	0
T99	10835	30	0	0
T100	7345	8	0	0
T101	13273	86	0	0
T102	7155	17	0	0
T103	2837	6	0	0
T104	11233	4	0	0
T105	2214	5	0	0
T119	1880	9	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1167	0	0
T97	3416	10	0	0
T98	14527	122	0	0
T99	10835	22	0	0
T100	7345	18	0	0
T101	13273	72	0	0
T102	7155	11	0	0
T103	2837	10	0	0
T104	11233	13	0	0
T105	2214	8	0	0
T119	1880	1	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1132	0	0
T97	3416	5	0	0
T98	14527	175	0	0
T99	10835	6	0	0
T100	7345	28	0	0
T101	13273	48	0	0
T102	7155	16	0	0
T103	2837	22	0	0
T104	11233	19	0	0
T105	2214	12	0	0
T119	1880	8	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1085	0	0
T97	3416	18	0	0
T98	14527	89	0	0
T99	10835	13	0	0
T100	7345	17	0	0
T101	13273	58	0	0
T102	7155	21	0	0
T103	2837	31	0	0
T104	11233	10	0	0
T105	2214	10	0	0
T106	3760	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1065	0	0
T97	3416	12	0	0
T98	14527	113	0	0
T99	10835	18	0	0
T100	7345	16	0	0
T101	13273	48	0	0
T102	7155	4	0	0
T103	2837	33	0	0
T104	11233	30	0	0
T105	2214	12	0	0
T106	3760	26	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406198472	1267	0	0
T97	3416	8	0	0
T98	14527	128	0	0
T99	10835	39	0	0
T100	7345	15	0	0
T101	13273	60	0	0
T102	7155	16	0	0
T103	2837	31	0	0
T104	11233	12	0	0
T105	2214	6	0	0
T119	1880	1	0	0