Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	333	1			T1	1		T3	8		T6	1
all_values[1]	333	1			T1	1		T3	8		T6	1
all_values[2]	333	1			T1	1		T3	8		T6	1
all_values[3]	333	1			T1	1		T3	8		T6	1
all_values[4]	333	1			T1	1		T3	8		T6	1
all_values[5]	333	1			T1	1		T3	8		T6	1
all_values[6]	333	1			T1	1		T3	8		T6	1
all_values[7]	333	1			T1	1		T3	8		T6	1
all_values[8]	333	1			T1	1		T3	8		T6	1
all_values[9]	333	1			T1	1		T3	8		T6	1
all_values[10]	333	1			T1	1		T3	8		T6	1
all_values[11]	333	1			T1	1		T3	8		T6	1
all_values[12]	333	1			T1	1		T3	8		T6	1
all_values[13]	333	1			T1	1		T3	8		T6	1
all_values[14]	333	1			T1	1		T3	8		T6	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3268

1

T1

15

T3

73

T6

15

auto[1]

1727

1

T3

47

T8

32

T12

54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T1

15

T3

12

T6

15

auto[1]

3880

1

T3

108

T8

64

T12

106

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	81	1			T1	1		T3	2		T6	1
all_values[0]	auto[0]	auto[1]	143	1			T3	3		T8	2		T12	4
all_values[0]	auto[1]	auto[1]	109	1			T3	3		T8	1		T12	2
all_values[1]	auto[0]	auto[0]	64	1			T1	1		T3	1		T6	1
all_values[1]	auto[0]	auto[1]	165	1			T3	4		T8	3		T12	5
all_values[1]	auto[1]	auto[1]	104	1			T3	3		T8	2		T12	2
all_values[2]	auto[0]	auto[0]	71	1			T1	1		T6	1		T8	5
all_values[2]	auto[0]	auto[1]	153	1			T3	7		T12	4		T13	2
all_values[2]	auto[1]	auto[1]	109	1			T3	1		T12	3		T13	1
all_values[3]	auto[0]	auto[0]	78	1			T1	1		T3	1		T6	1
all_values[3]	auto[0]	auto[1]	119	1			T3	5		T8	3		T12	1
all_values[3]	auto[1]	auto[1]	136	1			T3	2		T8	2		T12	7
all_values[4]	auto[0]	auto[0]	70	1			T1	1		T3	1		T6	1
all_values[4]	auto[0]	auto[1]	165	1			T3	6		T8	4		T12	5
all_values[4]	auto[1]	auto[1]	98	1			T3	1		T8	1		T12	2
all_values[5]	auto[0]	auto[0]	82	1			T1	1		T6	1		T7	1
all_values[5]	auto[0]	auto[1]	134	1			T3	4		T8	3		T12	1
all_values[5]	auto[1]	auto[1]	117	1			T3	4		T8	2		T12	3
all_values[6]	auto[0]	auto[0]	78	1			T1	1		T3	2		T6	1
all_values[6]	auto[0]	auto[1]	134	1			T3	3		T8	1		T12	3
all_values[6]	auto[1]	auto[1]	121	1			T3	3		T8	2		T12	5
all_values[7]	auto[0]	auto[0]	74	1			T1	1		T6	1		T8	1
all_values[7]	auto[0]	auto[1]	142	1			T3	5		T8	3		T12	4
all_values[7]	auto[1]	auto[1]	117	1			T3	3		T8	1		T12	4
all_values[8]	auto[0]	auto[0]	77	1			T1	1		T6	1		T7	1
all_values[8]	auto[0]	auto[1]	151	1			T3	4		T8	2		T12	4
all_values[8]	auto[1]	auto[1]	105	1			T3	4		T8	3		T12	4
all_values[9]	auto[0]	auto[0]	78	1			T1	1		T6	1		T7	1
all_values[9]	auto[0]	auto[1]	134	1			T3	3		T8	1		T12	3
all_values[9]	auto[1]	auto[1]	121	1			T3	5		T8	4		T12	5
all_values[10]	auto[0]	auto[0]	81	1			T1	1		T3	2		T6	1
all_values[10]	auto[0]	auto[1]	145	1			T3	4		T8	2		T12	5
all_values[10]	auto[1]	auto[1]	107	1			T3	2		T8	2		T12	2
all_values[11]	auto[0]	auto[0]	66	1			T1	1		T6	1		T7	1
all_values[11]	auto[0]	auto[1]	155	1			T3	5		T8	3		T12	4
all_values[11]	auto[1]	auto[1]	112	1			T3	3		T8	2		T12	4
all_values[12]	auto[0]	auto[0]	91	1			T1	1		T3	1		T6	1
all_values[12]	auto[0]	auto[1]	135	1			T3	3		T8	2		T12	3
all_values[12]	auto[1]	auto[1]	107	1			T3	4		T8	3		T12	4
all_values[13]	auto[0]	auto[0]	62	1			T1	1		T3	2		T6	1
all_values[13]	auto[0]	auto[1]	143	1			T3	4		T8	2		T12	4
all_values[13]	auto[1]	auto[1]	128	1			T3	2		T8	3		T12	3
all_values[14]	auto[0]	auto[0]	62	1			T1	1		T6	1		T7	1
all_values[14]	auto[0]	auto[1]	135	1			T3	1		T8	1		T12	2
all_values[14]	auto[1]	auto[1]	136	1			T3	7		T8	4		T12	4