| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 52.81 | 40.66 | 40.76 | 91.14 | 0.00 | 42.98 | 99.68 | 54.42 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 43.48 | 43.48 | 40.47 | 40.47 | 37.00 | 37.00 | 86.78 | 86.78 | 0.00 | 0.00 | 42.20 | 42.20 | 92.68 | 92.68 | 5.26 | 5.26 | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2590014593 |
| 48.40 | 4.92 | 40.59 | 0.12 | 38.54 | 1.54 | 90.27 | 3.49 | 0.00 | 0.00 | 42.84 | 0.64 | 93.31 | 0.64 | 33.26 | 28.00 | /workspace/coverage/cover_reg_top/31.i2c_intr_test.4164933785 |
| 50.81 | 2.41 | 40.62 | 0.03 | 39.71 | 1.17 | 91.52 | 1.25 | 0.00 | 0.00 | 42.91 | 0.07 | 98.73 | 5.41 | 42.21 | 8.95 | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3414451585 |
| 51.98 | 1.17 | 40.62 | 0.00 | 39.71 | 0.00 | 93.27 | 1.75 | 0.00 | 0.00 | 42.91 | 0.00 | 99.36 | 0.64 | 48.00 | 5.79 | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4040873587 |
| 52.78 | 0.80 | 40.66 | 0.03 | 40.01 | 0.30 | 97.51 | 4.24 | 0.00 | 0.00 | 42.98 | 0.07 | 99.36 | 0.00 | 48.95 | 0.95 | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4184559192 |
| 53.05 | 0.27 | 40.66 | 0.00 | 40.01 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.36 | 0.00 | 50.84 | 1.89 | /workspace/coverage/cover_reg_top/47.i2c_intr_test.3051807953 |
| 53.26 | 0.21 | 40.66 | 0.00 | 40.01 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.32 | 52.00 | 1.16 | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.145553561 |
| 53.40 | 0.14 | 40.66 | 0.00 | 40.01 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 52.95 | 0.95 | /workspace/coverage/cover_reg_top/29.i2c_intr_test.2983884189 |
| 53.49 | 0.09 | 40.66 | 0.00 | 40.01 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.58 | 0.63 | /workspace/coverage/cover_reg_top/39.i2c_intr_test.2822376683 |
| 53.54 | 0.05 | 40.66 | 0.00 | 40.27 | 0.26 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.68 | 0.11 | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3428243717 |
| 53.58 | 0.05 | 40.66 | 0.00 | 40.27 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.00 | 0.32 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2508640605 |
| 53.63 | 0.04 | 40.66 | 0.00 | 40.57 | 0.30 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.00 | 0.00 | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1725753921 |
| 53.66 | 0.03 | 40.66 | 0.00 | 40.57 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.21 | 0.21 | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1844054264 |
| 53.69 | 0.03 | 40.66 | 0.00 | 40.57 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.42 | 0.21 | /workspace/coverage/cover_reg_top/35.i2c_intr_test.1188143879 |
| 53.70 | 0.01 | 40.66 | 0.00 | 40.65 | 0.08 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.42 | 0.00 | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2143863154 |
| 53.70 | 0.01 | 40.66 | 0.00 | 40.68 | 0.04 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.42 | 0.00 | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1508301333 |
| 53.71 | 0.01 | 40.66 | 0.00 | 40.72 | 0.04 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.42 | 0.00 | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1617411911 |
| 53.71 | 0.01 | 40.66 | 0.00 | 40.76 | 0.04 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.42 | 0.00 | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.961839544 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1745806146 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.226175539 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.764970324 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1043873226 |
| /workspace/coverage/cover_reg_top/0.i2c_intr_test.1164032111 |
| /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3728071991 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3693221357 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.91286023 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3664552808 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1627839514 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1765562832 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2266973721 |
| /workspace/coverage/cover_reg_top/1.i2c_intr_test.2961744311 |
| /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.706448899 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2799654731 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.726272961 |
| /workspace/coverage/cover_reg_top/10.i2c_intr_test.1376974492 |
| /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2362736145 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_errors.495308892 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1556082069 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1099206880 |
| /workspace/coverage/cover_reg_top/11.i2c_intr_test.896552708 |
| /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.508777564 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3103073954 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1642127254 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3332566347 |
| /workspace/coverage/cover_reg_top/12.i2c_intr_test.2118992392 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_errors.492325377 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2127227155 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3139238484 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1466121831 |
| /workspace/coverage/cover_reg_top/13.i2c_intr_test.3261291662 |
| /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2703459952 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3493950162 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1644349910 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2930691668 |
| /workspace/coverage/cover_reg_top/14.i2c_intr_test.4231909830 |
| /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2486124778 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_errors.4160573895 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1603752147 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2039499624 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3387503138 |
| /workspace/coverage/cover_reg_top/15.i2c_intr_test.1046397513 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2936324605 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1729459097 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3360275246 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_rw.538899966 |
| /workspace/coverage/cover_reg_top/16.i2c_intr_test.1018171219 |
| /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1954122128 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_errors.837752183 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2831474931 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2606400182 |
| /workspace/coverage/cover_reg_top/17.i2c_intr_test.834974811 |
| /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1420587958 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1533922336 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2398280496 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3449263777 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_rw.4086207374 |
| /workspace/coverage/cover_reg_top/18.i2c_intr_test.1794421430 |
| /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1023694953 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1993822283 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1290766080 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3612483930 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3615791605 |
| /workspace/coverage/cover_reg_top/19.i2c_intr_test.2108654535 |
| /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.671695316 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2878979073 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1578945044 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2562738493 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1810964789 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2660634360 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_rw.913210628 |
| /workspace/coverage/cover_reg_top/2.i2c_intr_test.663474550 |
| /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2567237496 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1187010507 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1124215672 |
| /workspace/coverage/cover_reg_top/20.i2c_intr_test.2193874203 |
| /workspace/coverage/cover_reg_top/21.i2c_intr_test.1363322991 |
| /workspace/coverage/cover_reg_top/22.i2c_intr_test.3723423231 |
| /workspace/coverage/cover_reg_top/23.i2c_intr_test.3112075806 |
| /workspace/coverage/cover_reg_top/24.i2c_intr_test.3373675868 |
| /workspace/coverage/cover_reg_top/25.i2c_intr_test.3451908574 |
| /workspace/coverage/cover_reg_top/26.i2c_intr_test.854264800 |
| /workspace/coverage/cover_reg_top/27.i2c_intr_test.3970073012 |
| /workspace/coverage/cover_reg_top/28.i2c_intr_test.1620198658 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3144700752 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3462608897 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3123952810 |
| /workspace/coverage/cover_reg_top/3.i2c_intr_test.3408396827 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_errors.988580692 |
| /workspace/coverage/cover_reg_top/30.i2c_intr_test.1625222533 |
| /workspace/coverage/cover_reg_top/32.i2c_intr_test.2855104854 |
| /workspace/coverage/cover_reg_top/33.i2c_intr_test.2764235099 |
| /workspace/coverage/cover_reg_top/34.i2c_intr_test.1879880689 |
| /workspace/coverage/cover_reg_top/36.i2c_intr_test.4115348723 |
| /workspace/coverage/cover_reg_top/37.i2c_intr_test.3270387080 |
| /workspace/coverage/cover_reg_top/38.i2c_intr_test.4031122303 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.987969551 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3184337855 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3277424176 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1636610998 |
| /workspace/coverage/cover_reg_top/4.i2c_intr_test.3503064662 |
| /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.769822988 |
| /workspace/coverage/cover_reg_top/4.i2c_tl_errors.4104803471 |
| /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2863460776 |
| /workspace/coverage/cover_reg_top/40.i2c_intr_test.1562333065 |
| /workspace/coverage/cover_reg_top/41.i2c_intr_test.2327038533 |
| /workspace/coverage/cover_reg_top/42.i2c_intr_test.3692669157 |
| /workspace/coverage/cover_reg_top/43.i2c_intr_test.574774911 |
| /workspace/coverage/cover_reg_top/44.i2c_intr_test.2821892558 |
| /workspace/coverage/cover_reg_top/45.i2c_intr_test.1521537949 |
| /workspace/coverage/cover_reg_top/46.i2c_intr_test.2727478490 |
| /workspace/coverage/cover_reg_top/48.i2c_intr_test.3744238029 |
| /workspace/coverage/cover_reg_top/49.i2c_intr_test.2662748075 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.823466553 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3666408454 |
| /workspace/coverage/cover_reg_top/5.i2c_intr_test.266804408 |
| /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1371924905 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3076715335 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1256382970 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4233456744 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3838977700 |
| /workspace/coverage/cover_reg_top/6.i2c_intr_test.2877012298 |
| /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3810650030 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1569023733 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2189384990 |
| /workspace/coverage/cover_reg_top/7.i2c_intr_test.3154334698 |
| /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2552251326 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2568963560 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.596369012 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2161978020 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3277390722 |
| /workspace/coverage/cover_reg_top/8.i2c_intr_test.2694649510 |
| /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.860999655 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1880114247 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3497451535 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3210450861 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1229419311 |
| /workspace/coverage/cover_reg_top/9.i2c_intr_test.2188781410 |
| /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1481566200 |
| /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4095202031 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4095202031 | Jun 09 12:24:23 PM PDT 24 | Jun 09 12:24:26 PM PDT 24 | 912769115 ps | ||
| T2 | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2590014593 | Jun 09 12:24:17 PM PDT 24 | Jun 09 12:24:18 PM PDT 24 | 15771725 ps | ||
| T3 | /workspace/coverage/cover_reg_top/31.i2c_intr_test.4164933785 | Jun 09 12:24:35 PM PDT 24 | Jun 09 12:24:37 PM PDT 24 | 94831116 ps | ||
| T6 | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2568963560 | Jun 09 12:24:23 PM PDT 24 | Jun 09 12:24:26 PM PDT 24 | 66396318 ps | ||
| T8 | /workspace/coverage/cover_reg_top/42.i2c_intr_test.3692669157 | Jun 09 12:24:46 PM PDT 24 | Jun 09 12:24:47 PM PDT 24 | 18452449 ps | ||
| T7 | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3414451585 | Jun 09 12:24:27 PM PDT 24 | Jun 09 12:24:29 PM PDT 24 | 119995749 ps | ||
| T12 | /workspace/coverage/cover_reg_top/48.i2c_intr_test.3744238029 | Jun 09 12:24:52 PM PDT 24 | Jun 09 12:24:53 PM PDT 24 | 18108652 ps | ||
| T9 | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.961839544 | Jun 09 12:24:30 PM PDT 24 | Jun 09 12:24:32 PM PDT 24 | 46548584 ps | ||
| T13 | /workspace/coverage/cover_reg_top/39.i2c_intr_test.2822376683 | Jun 09 12:24:36 PM PDT 24 | Jun 09 12:24:38 PM PDT 24 | 70372448 ps | ||
| T14 | /workspace/coverage/cover_reg_top/21.i2c_intr_test.1363322991 | Jun 09 12:24:40 PM PDT 24 | Jun 09 12:24:42 PM PDT 24 | 38579400 ps | ||
| T10 | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.145553561 | Jun 09 12:24:27 PM PDT 24 | Jun 09 12:24:28 PM PDT 24 | 63121169 ps | ||
| T15 | /workspace/coverage/cover_reg_top/15.i2c_intr_test.1046397513 | Jun 09 12:24:28 PM PDT 24 | Jun 09 12:24:29 PM PDT 24 | 65564935 ps | ||
| T26 | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2562738493 | Jun 09 12:24:23 PM PDT 24 | Jun 09 12:24:25 PM PDT 24 | 218745603 ps | ||
| T16 | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2878979073 | Jun 09 12:24:36 PM PDT 24 | Jun 09 12:24:38 PM PDT 24 | 45771975 ps | ||
| T11 | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2567237496 | Jun 09 12:24:18 PM PDT 24 | Jun 09 12:24:19 PM PDT 24 | 37029665 ps | ||
| T43 | /workspace/coverage/cover_reg_top/29.i2c_intr_test.2983884189 | Jun 09 12:24:37 PM PDT 24 | Jun 09 12:24:38 PM PDT 24 | 21945737 ps | ||
| T44 | /workspace/coverage/cover_reg_top/18.i2c_intr_test.1794421430 | Jun 09 12:24:36 PM PDT 24 | Jun 09 12:24:38 PM PDT 24 | 18496214 ps | ||
| T4 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2508640605 | Jun 09 12:24:18 PM PDT 24 | Jun 09 12:24:20 PM PDT 24 | 30400083 ps | ||
| T37 | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.769822988 | Jun 09 12:24:14 PM PDT 24 | Jun 09 12:24:16 PM PDT 24 | 146208999 ps | ||
| T5 | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3184337855 | Jun 09 12:24:21 PM PDT 24 | Jun 09 12:24:23 PM PDT 24 | 60602985 ps | ||
| T27 | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1745806146 | Jun 09 12:24:08 PM PDT 24 | Jun 09 12:24:11 PM PDT 24 | 142326187 ps | ||
| T28 | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2552251326 | Jun 09 12:24:23 PM PDT 24 | Jun 09 12:24:24 PM PDT 24 | 29982840 ps | ||
| T38 | /workspace/coverage/cover_reg_top/47.i2c_intr_test.3051807953 | Jun 09 12:24:42 PM PDT 24 | Jun 09 12:24:43 PM PDT 24 | 20649018 ps | ||
| T29 | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3144700752 | Jun 09 12:24:17 PM PDT 24 | Jun 09 12:24:19 PM PDT 24 | 112644022 ps | ||
| T25 | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1729459097 | Jun 09 12:24:28 PM PDT 24 | Jun 09 12:24:30 PM PDT 24 | 206964625 ps | ||
| T39 | /workspace/coverage/cover_reg_top/34.i2c_intr_test.1879880689 | Jun 09 12:24:38 PM PDT 24 | Jun 09 12:24:39 PM PDT 24 | 48200998 ps | ||
| T17 | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3449263777 | Jun 09 12:24:40 PM PDT 24 | Jun 09 12:24:42 PM PDT 24 | 157641511 ps | ||
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| T18 | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3277424176 | Jun 09 12:24:25 PM PDT 24 | Jun 09 12:24:27 PM PDT 24 | 47847056 ps | ||
| T30 | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4040873587 | Jun 09 12:24:27 PM PDT 24 | Jun 09 12:24:34 PM PDT 24 | 662576604 ps | ||
| T19 | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3612483930 | Jun 09 12:24:36 PM PDT 24 | Jun 09 12:24:39 PM PDT 24 | 82983167 ps | ||
| T20 | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3462608897 | Jun 09 12:24:25 PM PDT 24 | Jun 09 12:24:27 PM PDT 24 | 83053107 ps | ||
| T21 | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.823466553 | Jun 09 12:24:22 PM PDT 24 | Jun 09 12:24:24 PM PDT 24 | 20102090 ps | ||
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| T31 | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.226175539 | Jun 09 12:24:13 PM PDT 24 | Jun 09 12:24:17 PM PDT 24 | 330784717 ps | ||
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| T22 | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3139238484 | Jun 09 12:24:30 PM PDT 24 | Jun 09 12:24:32 PM PDT 24 | 121384096 ps | ||
| T23 | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1993822283 | Jun 09 12:24:37 PM PDT 24 | Jun 09 12:24:39 PM PDT 24 | 153783381 ps | ||
| T32 | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.913210628 | Jun 09 12:24:16 PM PDT 24 | Jun 09 12:24:17 PM PDT 24 | 81242302 ps | ||
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| T46 | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2362736145 | Jun 09 12:24:28 PM PDT 24 | Jun 09 12:24:30 PM PDT 24 | 360775326 ps | ||
| T78 | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2660634360 | Jun 09 12:24:17 PM PDT 24 | Jun 09 12:24:19 PM PDT 24 | 35255098 ps | ||
| T49 | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4184559192 | Jun 09 12:24:22 PM PDT 24 | Jun 09 12:24:25 PM PDT 24 | 154341451 ps | ||
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| T79 | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3360275246 | Jun 09 12:24:38 PM PDT 24 | Jun 09 12:24:40 PM PDT 24 | 104804725 ps | ||
| T53 | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3497451535 | Jun 09 12:24:27 PM PDT 24 | Jun 09 12:24:31 PM PDT 24 | 612934872 ps | ||
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| T47 | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1371924905 | Jun 09 12:24:27 PM PDT 24 | Jun 09 12:24:28 PM PDT 24 | 19788305 ps | ||
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| T82 | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.706448899 | Jun 09 12:24:20 PM PDT 24 | Jun 09 12:24:22 PM PDT 24 | 30678246 ps | ||
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| T85 | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.91286023 | Jun 09 12:24:10 PM PDT 24 | Jun 09 12:24:12 PM PDT 24 | 54917007 ps | ||
| T86 | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.764970324 | Jun 09 12:24:08 PM PDT 24 | Jun 09 12:24:10 PM PDT 24 | 45407926 ps | ||
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| T95 | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3810650030 | Jun 09 12:24:20 PM PDT 24 | Jun 09 12:24:22 PM PDT 24 | 60861236 ps | ||
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| T98 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3728071991 | Jun 09 12:24:08 PM PDT 24 | Jun 09 12:24:10 PM PDT 24 | 33891895 ps | ||
| T41 | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.987969551 | Jun 09 12:24:24 PM PDT 24 | Jun 09 12:24:27 PM PDT 24 | 606796727 ps | ||
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| T104 | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3210450861 | Jun 09 12:24:25 PM PDT 24 | Jun 09 12:24:27 PM PDT 24 | 273988190 ps | ||
| T105 | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2161978020 | Jun 09 12:24:19 PM PDT 24 | Jun 09 12:24:21 PM PDT 24 | 30729883 ps | ||
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| T107 | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3664552808 | Jun 09 12:24:11 PM PDT 24 | Jun 09 12:24:14 PM PDT 24 | 337849763 ps | ||
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| T115 | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2703459952 | Jun 09 12:24:34 PM PDT 24 | Jun 09 12:24:35 PM PDT 24 | 183719112 ps | ||
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| T118 | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1642127254 | Jun 09 12:24:27 PM PDT 24 | Jun 09 12:24:28 PM PDT 24 | 132602149 ps | ||
| T52 | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.596369012 | Jun 09 12:24:31 PM PDT 24 | Jun 09 12:24:34 PM PDT 24 | 160291816 ps | ||
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| T63 | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1420587958 | Jun 09 12:24:36 PM PDT 24 | Jun 09 12:24:38 PM PDT 24 | 37575475 ps | ||
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| T65 | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1627839514 | Jun 09 12:24:16 PM PDT 24 | Jun 09 12:24:17 PM PDT 24 | 151804955 ps | ||
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| T145 | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1569023733 | Jun 09 12:24:22 PM PDT 24 | Jun 09 12:24:23 PM PDT 24 | 26495525 ps | ||
| T146 | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.4104803471 | Jun 09 12:24:20 PM PDT 24 | Jun 09 12:24:22 PM PDT 24 | 353525083 ps | ||
| T147 | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2486124778 | Jun 09 12:24:28 PM PDT 24 | Jun 09 12:24:30 PM PDT 24 | 106540089 ps | ||
| T148 | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.726272961 | Jun 09 12:24:31 PM PDT 24 | Jun 09 12:24:33 PM PDT 24 | 147368137 ps | ||
| T149 | /workspace/coverage/cover_reg_top/13.i2c_intr_test.3261291662 | Jun 09 12:24:32 PM PDT 24 | Jun 09 12:24:33 PM PDT 24 | 15222578 ps | ||
| T150 | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3123952810 | Jun 09 12:24:18 PM PDT 24 | Jun 09 12:24:19 PM PDT 24 | 20290500 ps | ||
| T151 | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1880114247 | Jun 09 12:24:29 PM PDT 24 | Jun 09 12:24:30 PM PDT 24 | 195383411 ps | ||
| T152 | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2936324605 | Jun 09 12:24:27 PM PDT 24 | Jun 09 12:24:30 PM PDT 24 | 150330225 ps | ||
| T153 | /workspace/coverage/cover_reg_top/40.i2c_intr_test.1562333065 | Jun 09 12:24:42 PM PDT 24 | Jun 09 12:24:43 PM PDT 24 | 33626790 ps | ||
| T154 | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2127227155 | Jun 09 12:24:27 PM PDT 24 | Jun 09 12:24:30 PM PDT 24 | 138384911 ps | ||
| T155 | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3693221357 | Jun 09 12:24:11 PM PDT 24 | Jun 09 12:24:13 PM PDT 24 | 94444708 ps | ||
| T156 | /workspace/coverage/cover_reg_top/36.i2c_intr_test.4115348723 | Jun 09 12:24:34 PM PDT 24 | Jun 09 12:24:35 PM PDT 24 | 18365512 ps | ||
| T157 | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1765562832 | Jun 09 12:24:10 PM PDT 24 | Jun 09 12:24:11 PM PDT 24 | 73407652 ps | ||
| T158 | /workspace/coverage/cover_reg_top/26.i2c_intr_test.854264800 | Jun 09 12:24:35 PM PDT 24 | Jun 09 12:24:37 PM PDT 24 | 22191951 ps | ||
| T159 | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1466121831 | Jun 09 12:24:28 PM PDT 24 | Jun 09 12:24:29 PM PDT 24 | 18672768 ps |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2590014593 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15771725 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:17 PM PDT 24 |
| Finished | Jun 09 12:24:18 PM PDT 24 |
| Peak memory | 203628 kb |
| Host | smart-7834604d-2e2c-40bf-8abf-300e1d313259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590014593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2590014593 |
| Directory | /workspace/3.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.i2c_intr_test.4164933785 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 94831116 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:37 PM PDT 24 |
| Peak memory | 203560 kb |
| Host | smart-863e89ce-6f6b-4a25-aaba-7a93715cfa7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164933785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.4164933785 |
| Directory | /workspace/31.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3414451585 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 119995749 ps |
| CPU time | 1.53 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:29 PM PDT 24 |
| Peak memory | 203876 kb |
| Host | smart-1ae1b5fb-d694-4873-ae07-9359721e2300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414451585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3414451585 |
| Directory | /workspace/6.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4040873587 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 662576604 ps |
| CPU time | 6.15 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:34 PM PDT 24 |
| Peak memory | 203800 kb |
| Host | smart-ef9d2169-e805-4376-bf73-01a66b9b4031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040873587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.4040873587 |
| Directory | /workspace/3.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4184559192 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 154341451 ps |
| CPU time | 2.51 seconds |
| Started | Jun 09 12:24:22 PM PDT 24 |
| Finished | Jun 09 12:24:25 PM PDT 24 |
| Peak memory | 203784 kb |
| Host | smart-5032dda5-987a-427b-9e9a-42b82556562b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184559192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4184559192 |
| Directory | /workspace/6.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/47.i2c_intr_test.3051807953 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 20649018 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 12:24:42 PM PDT 24 |
| Finished | Jun 09 12:24:43 PM PDT 24 |
| Peak memory | 203556 kb |
| Host | smart-da51fa95-e04e-4f1c-b880-7184dbd63d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051807953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3051807953 |
| Directory | /workspace/47.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.145553561 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 63121169 ps |
| CPU time | 1.2 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:28 PM PDT 24 |
| Peak memory | 203864 kb |
| Host | smart-22ed4bee-f299-4379-b317-c7e8bac0c3b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145553561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou tstanding.145553561 |
| Directory | /workspace/12.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/29.i2c_intr_test.2983884189 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 21945737 ps |
| CPU time | 0.74 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-8ab34128-2350-4dc7-baa2-68e5c2ce5996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983884189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2983884189 |
| Directory | /workspace/29.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.i2c_intr_test.2822376683 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 70372448 ps |
| CPU time | 0.61 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203528 kb |
| Host | smart-049ba151-3a2d-4f60-b2d5-8cba686269f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822376683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2822376683 |
| Directory | /workspace/39.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3428243717 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 88228484 ps |
| CPU time | 2.36 seconds |
| Started | Jun 09 12:24:09 PM PDT 24 |
| Finished | Jun 09 12:24:12 PM PDT 24 |
| Peak memory | 203880 kb |
| Host | smart-f9663885-89a8-44a5-98d2-f99a7859a62f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428243717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3428243717 |
| Directory | /workspace/0.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2508640605 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30400083 ps |
| CPU time | 0.8 seconds |
| Started | Jun 09 12:24:18 PM PDT 24 |
| Finished | Jun 09 12:24:20 PM PDT 24 |
| Peak memory | 203620 kb |
| Host | smart-7a180067-55b9-4ae5-8d0f-fe5565fdd752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508640605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2508640605 |
| Directory | /workspace/0.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1725753921 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 62573284 ps |
| CPU time | 1.55 seconds |
| Started | Jun 09 12:24:25 PM PDT 24 |
| Finished | Jun 09 12:24:28 PM PDT 24 |
| Peak memory | 203896 kb |
| Host | smart-325d041c-6cca-4a73-95ed-1362202cf297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725753921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1725753921 |
| Directory | /workspace/13.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1844054264 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 545640974 ps |
| CPU time | 1.74 seconds |
| Started | Jun 09 12:24:46 PM PDT 24 |
| Finished | Jun 09 12:24:48 PM PDT 24 |
| Peak memory | 203612 kb |
| Host | smart-9b1b5fe5-8ba5-4061-af81-93d65f575a3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844054264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1844054264 |
| Directory | /workspace/10.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/35.i2c_intr_test.1188143879 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 17485528 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:38 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-f5a768ae-862d-44f8-b971-6d6f8220a9b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188143879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1188143879 |
| Directory | /workspace/35.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2143863154 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 82314255 ps |
| CPU time | 1.58 seconds |
| Started | Jun 09 12:24:29 PM PDT 24 |
| Finished | Jun 09 12:24:31 PM PDT 24 |
| Peak memory | 203884 kb |
| Host | smart-e861bc77-e35d-4b41-ad2a-c625f36ed112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143863154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2143863154 |
| Directory | /workspace/11.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1508301333 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1345318674 ps |
| CPU time | 2.62 seconds |
| Started | Jun 09 12:24:19 PM PDT 24 |
| Finished | Jun 09 12:24:22 PM PDT 24 |
| Peak memory | 203812 kb |
| Host | smart-d5d1f064-8e2e-427d-8116-91605cb09c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508301333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1508301333 |
| Directory | /workspace/1.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1617411911 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 49261173 ps |
| CPU time | 1.47 seconds |
| Started | Jun 09 12:24:28 PM PDT 24 |
| Finished | Jun 09 12:24:30 PM PDT 24 |
| Peak memory | 203884 kb |
| Host | smart-bb5c9489-9e8b-44aa-a983-5dc3b8561fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617411911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1617411911 |
| Directory | /workspace/10.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.961839544 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 46548584 ps |
| CPU time | 1.18 seconds |
| Started | Jun 09 12:24:30 PM PDT 24 |
| Finished | Jun 09 12:24:32 PM PDT 24 |
| Peak memory | 203872 kb |
| Host | smart-b4133fc3-0304-4f00-9cba-d3b3b61e65e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961839544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou tstanding.961839544 |
| Directory | /workspace/15.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1745806146 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 142326187 ps |
| CPU time | 2.24 seconds |
| Started | Jun 09 12:24:08 PM PDT 24 |
| Finished | Jun 09 12:24:11 PM PDT 24 |
| Peak memory | 203784 kb |
| Host | smart-2ab5ef1e-6d2f-4757-abbc-312cfa2c403a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745806146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1745806146 |
| Directory | /workspace/0.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.226175539 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 330784717 ps |
| CPU time | 3.52 seconds |
| Started | Jun 09 12:24:13 PM PDT 24 |
| Finished | Jun 09 12:24:17 PM PDT 24 |
| Peak memory | 203832 kb |
| Host | smart-90b33a68-253b-46d6-a8d2-03bf842ed850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226175539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.226175539 |
| Directory | /workspace/0.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.764970324 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 45407926 ps |
| CPU time | 1.15 seconds |
| Started | Jun 09 12:24:08 PM PDT 24 |
| Finished | Jun 09 12:24:10 PM PDT 24 |
| Peak memory | 203940 kb |
| Host | smart-2aa6dba4-156e-4db8-b280-56377ef1632d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764970324 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.764970324 |
| Directory | /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1043873226 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 76893287 ps |
| CPU time | 0.75 seconds |
| Started | Jun 09 12:24:08 PM PDT 24 |
| Finished | Jun 09 12:24:10 PM PDT 24 |
| Peak memory | 203616 kb |
| Host | smart-6d645b73-6c8b-4354-ba61-5573aad050e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043873226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1043873226 |
| Directory | /workspace/0.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_intr_test.1164032111 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 54491511 ps |
| CPU time | 0.63 seconds |
| Started | Jun 09 12:24:14 PM PDT 24 |
| Finished | Jun 09 12:24:15 PM PDT 24 |
| Peak memory | 203532 kb |
| Host | smart-059c4a62-e503-4565-bf49-ff6ccfa439e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164032111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1164032111 |
| Directory | /workspace/0.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3728071991 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 33891895 ps |
| CPU time | 0.84 seconds |
| Started | Jun 09 12:24:08 PM PDT 24 |
| Finished | Jun 09 12:24:10 PM PDT 24 |
| Peak memory | 203632 kb |
| Host | smart-44fdd100-69de-48ed-b6e5-7d8da70d402b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728071991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.3728071991 |
| Directory | /workspace/0.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3693221357 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 94444708 ps |
| CPU time | 1.33 seconds |
| Started | Jun 09 12:24:11 PM PDT 24 |
| Finished | Jun 09 12:24:13 PM PDT 24 |
| Peak memory | 203832 kb |
| Host | smart-c0b1cb03-2625-4464-8c54-0c51ee86a584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693221357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3693221357 |
| Directory | /workspace/0.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.91286023 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 54917007 ps |
| CPU time | 1.36 seconds |
| Started | Jun 09 12:24:10 PM PDT 24 |
| Finished | Jun 09 12:24:12 PM PDT 24 |
| Peak memory | 203816 kb |
| Host | smart-ae2802e7-b956-40a4-a491-c3740567a46a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91286023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.91286023 |
| Directory | /workspace/1.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3664552808 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 337849763 ps |
| CPU time | 2.83 seconds |
| Started | Jun 09 12:24:11 PM PDT 24 |
| Finished | Jun 09 12:24:14 PM PDT 24 |
| Peak memory | 203892 kb |
| Host | smart-fb2a5265-acbb-4a93-8943-83f04171ffe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664552808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3664552808 |
| Directory | /workspace/1.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1627839514 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 151804955 ps |
| CPU time | 0.79 seconds |
| Started | Jun 09 12:24:16 PM PDT 24 |
| Finished | Jun 09 12:24:17 PM PDT 24 |
| Peak memory | 203640 kb |
| Host | smart-61033dbf-9b2e-4302-969f-021ed984162f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627839514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1627839514 |
| Directory | /workspace/1.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1765562832 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 73407652 ps |
| CPU time | 0.87 seconds |
| Started | Jun 09 12:24:10 PM PDT 24 |
| Finished | Jun 09 12:24:11 PM PDT 24 |
| Peak memory | 203708 kb |
| Host | smart-942e535f-bf48-40b9-b7c5-757b9ed5d28d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765562832 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1765562832 |
| Directory | /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2266973721 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 18703066 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:13 PM PDT 24 |
| Finished | Jun 09 12:24:14 PM PDT 24 |
| Peak memory | 203640 kb |
| Host | smart-4f9460bc-fa78-4563-b39e-625f833ff22c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266973721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2266973721 |
| Directory | /workspace/1.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_intr_test.2961744311 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 17370754 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 12:24:09 PM PDT 24 |
| Finished | Jun 09 12:24:10 PM PDT 24 |
| Peak memory | 203556 kb |
| Host | smart-7e3538ff-4fa1-46d9-9391-a33052824f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961744311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2961744311 |
| Directory | /workspace/1.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.706448899 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 30678246 ps |
| CPU time | 0.86 seconds |
| Started | Jun 09 12:24:20 PM PDT 24 |
| Finished | Jun 09 12:24:22 PM PDT 24 |
| Peak memory | 203632 kb |
| Host | smart-a69e37db-ae1e-4eab-b712-672040686d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706448899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out standing.706448899 |
| Directory | /workspace/1.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2799654731 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 59013916 ps |
| CPU time | 1.35 seconds |
| Started | Jun 09 12:24:09 PM PDT 24 |
| Finished | Jun 09 12:24:11 PM PDT 24 |
| Peak memory | 203872 kb |
| Host | smart-b441ad7f-d369-4331-b632-5afabac95126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799654731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2799654731 |
| Directory | /workspace/1.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.726272961 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 147368137 ps |
| CPU time | 0.8 seconds |
| Started | Jun 09 12:24:31 PM PDT 24 |
| Finished | Jun 09 12:24:33 PM PDT 24 |
| Peak memory | 203656 kb |
| Host | smart-336b25a4-0566-4080-9933-77c8453ee821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726272961 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.726272961 |
| Directory | /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_intr_test.1376974492 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 49922857 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 12:24:26 PM PDT 24 |
| Finished | Jun 09 12:24:27 PM PDT 24 |
| Peak memory | 203564 kb |
| Host | smart-8b8d9926-0dce-4169-b088-90693de20fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376974492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1376974492 |
| Directory | /workspace/10.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2362736145 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 360775326 ps |
| CPU time | 1.28 seconds |
| Started | Jun 09 12:24:28 PM PDT 24 |
| Finished | Jun 09 12:24:30 PM PDT 24 |
| Peak memory | 203800 kb |
| Host | smart-8d3b435e-2136-49a5-9def-cae5b57b3aa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362736145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.2362736145 |
| Directory | /workspace/10.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.495308892 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 42192213 ps |
| CPU time | 2.18 seconds |
| Started | Jun 09 12:24:30 PM PDT 24 |
| Finished | Jun 09 12:24:33 PM PDT 24 |
| Peak memory | 203872 kb |
| Host | smart-ce349447-ed54-4148-b0ae-6670bf8cf29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495308892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.495308892 |
| Directory | /workspace/10.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1556082069 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 42736829 ps |
| CPU time | 1.06 seconds |
| Started | Jun 09 12:24:30 PM PDT 24 |
| Finished | Jun 09 12:24:31 PM PDT 24 |
| Peak memory | 203700 kb |
| Host | smart-2a5f033e-b20a-4312-b2ef-7563b3e9eb31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556082069 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1556082069 |
| Directory | /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1099206880 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 17577367 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 12:24:38 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203668 kb |
| Host | smart-a979aa02-0eb2-41e9-896e-5f1ff69ac311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099206880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1099206880 |
| Directory | /workspace/11.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_intr_test.896552708 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 43686080 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:31 PM PDT 24 |
| Finished | Jun 09 12:24:32 PM PDT 24 |
| Peak memory | 203552 kb |
| Host | smart-bab63b6e-d0c6-4b43-b55c-5c8fffd322cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896552708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.896552708 |
| Directory | /workspace/11.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.508777564 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 123774705 ps |
| CPU time | 0.99 seconds |
| Started | Jun 09 12:24:30 PM PDT 24 |
| Finished | Jun 09 12:24:31 PM PDT 24 |
| Peak memory | 203620 kb |
| Host | smart-b0b30b0a-820f-460a-ba78-09028b21ed0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508777564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou tstanding.508777564 |
| Directory | /workspace/11.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3103073954 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 384214756 ps |
| CPU time | 1.23 seconds |
| Started | Jun 09 12:24:45 PM PDT 24 |
| Finished | Jun 09 12:24:47 PM PDT 24 |
| Peak memory | 203924 kb |
| Host | smart-ae0250c7-7255-41c3-8e44-685283f1e7f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103073954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3103073954 |
| Directory | /workspace/11.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1642127254 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 132602149 ps |
| CPU time | 0.98 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:28 PM PDT 24 |
| Peak memory | 203736 kb |
| Host | smart-bf08d888-3bf5-48a1-a951-28ebce17e0c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642127254 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1642127254 |
| Directory | /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3332566347 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 58807373 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:31 PM PDT 24 |
| Finished | Jun 09 12:24:33 PM PDT 24 |
| Peak memory | 203612 kb |
| Host | smart-99b58aec-fdfa-4531-8901-6be5ea603520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332566347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3332566347 |
| Directory | /workspace/12.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_intr_test.2118992392 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 42401041 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:28 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-7cc02e73-7dc9-4076-8d07-2682289f9a58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118992392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2118992392 |
| Directory | /workspace/12.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.492325377 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 306427603 ps |
| CPU time | 1.89 seconds |
| Started | Jun 09 12:24:32 PM PDT 24 |
| Finished | Jun 09 12:24:34 PM PDT 24 |
| Peak memory | 203888 kb |
| Host | smart-8b944e43-57fe-45b8-9920-70364807ba77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492325377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.492325377 |
| Directory | /workspace/12.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2127227155 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 138384911 ps |
| CPU time | 1.51 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:30 PM PDT 24 |
| Peak memory | 203904 kb |
| Host | smart-656559a9-e8f1-46a7-96d4-ed966acc7eb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127227155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2127227155 |
| Directory | /workspace/12.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3139238484 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 121384096 ps |
| CPU time | 1.01 seconds |
| Started | Jun 09 12:24:30 PM PDT 24 |
| Finished | Jun 09 12:24:32 PM PDT 24 |
| Peak memory | 203664 kb |
| Host | smart-17a25eb4-d503-485a-8848-ffbf3ac911f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139238484 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3139238484 |
| Directory | /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1466121831 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 18672768 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 12:24:28 PM PDT 24 |
| Finished | Jun 09 12:24:29 PM PDT 24 |
| Peak memory | 203636 kb |
| Host | smart-591ab189-ade3-48cd-a2e9-fa496c2e9777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466121831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1466121831 |
| Directory | /workspace/13.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_intr_test.3261291662 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 15222578 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:32 PM PDT 24 |
| Finished | Jun 09 12:24:33 PM PDT 24 |
| Peak memory | 203568 kb |
| Host | smart-48322f03-3f5d-41d6-8dff-d0432f27ff87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261291662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3261291662 |
| Directory | /workspace/13.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2703459952 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 183719112 ps |
| CPU time | 1.23 seconds |
| Started | Jun 09 12:24:34 PM PDT 24 |
| Finished | Jun 09 12:24:35 PM PDT 24 |
| Peak memory | 203844 kb |
| Host | smart-d5599a20-11e5-4f0b-9787-fa846d34f201 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703459952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.2703459952 |
| Directory | /workspace/13.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3493950162 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 129817133 ps |
| CPU time | 2.34 seconds |
| Started | Jun 09 12:24:46 PM PDT 24 |
| Finished | Jun 09 12:24:49 PM PDT 24 |
| Peak memory | 203876 kb |
| Host | smart-081f412c-3024-458e-b823-0bfd21f3d2c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493950162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3493950162 |
| Directory | /workspace/13.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1644349910 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 32691932 ps |
| CPU time | 1.61 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:40 PM PDT 24 |
| Peak memory | 203880 kb |
| Host | smart-1e1ee957-9602-472e-a5ab-fc130ddf4faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644349910 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1644349910 |
| Directory | /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2930691668 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 26020191 ps |
| CPU time | 0.84 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:36 PM PDT 24 |
| Peak memory | 203668 kb |
| Host | smart-abc95e94-c215-4f83-86c0-a64d38153fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930691668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2930691668 |
| Directory | /workspace/14.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_intr_test.4231909830 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 64791818 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 12:24:29 PM PDT 24 |
| Finished | Jun 09 12:24:30 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-14dcec7c-efea-4545-88f3-b43b5c2f11c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231909830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.4231909830 |
| Directory | /workspace/14.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2486124778 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 106540089 ps |
| CPU time | 0.87 seconds |
| Started | Jun 09 12:24:28 PM PDT 24 |
| Finished | Jun 09 12:24:30 PM PDT 24 |
| Peak memory | 203560 kb |
| Host | smart-6083f25d-e4a4-4d40-8ea9-2583cf1dbe01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486124778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o utstanding.2486124778 |
| Directory | /workspace/14.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.4160573895 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 514601822 ps |
| CPU time | 2.47 seconds |
| Started | Jun 09 12:25:02 PM PDT 24 |
| Finished | Jun 09 12:25:05 PM PDT 24 |
| Peak memory | 203908 kb |
| Host | smart-b011c473-c535-4808-823e-9cd7fc171bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160573895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.4160573895 |
| Directory | /workspace/14.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1603752147 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 614924988 ps |
| CPU time | 2.48 seconds |
| Started | Jun 09 12:24:38 PM PDT 24 |
| Finished | Jun 09 12:24:42 PM PDT 24 |
| Peak memory | 203876 kb |
| Host | smart-9a6f8834-4d23-43c5-b98b-9d06f7941d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603752147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1603752147 |
| Directory | /workspace/14.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2039499624 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 92066584 ps |
| CPU time | 0.91 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203744 kb |
| Host | smart-c363f4d4-b6cf-4240-9ce5-d0d5b0edf224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039499624 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2039499624 |
| Directory | /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3387503138 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 44743683 ps |
| CPU time | 0.72 seconds |
| Started | Jun 09 12:24:53 PM PDT 24 |
| Finished | Jun 09 12:24:54 PM PDT 24 |
| Peak memory | 203664 kb |
| Host | smart-aaa16135-62de-4996-859c-126cdea36012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387503138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3387503138 |
| Directory | /workspace/15.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_intr_test.1046397513 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 65564935 ps |
| CPU time | 0.71 seconds |
| Started | Jun 09 12:24:28 PM PDT 24 |
| Finished | Jun 09 12:24:29 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-6a448eaa-5002-4153-b52b-ab3008883fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046397513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1046397513 |
| Directory | /workspace/15.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2936324605 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 150330225 ps |
| CPU time | 2.25 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:30 PM PDT 24 |
| Peak memory | 212116 kb |
| Host | smart-d95d7c4a-4736-41f0-841f-cf822d5fc209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936324605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2936324605 |
| Directory | /workspace/15.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1729459097 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 206964625 ps |
| CPU time | 1.39 seconds |
| Started | Jun 09 12:24:28 PM PDT 24 |
| Finished | Jun 09 12:24:30 PM PDT 24 |
| Peak memory | 203884 kb |
| Host | smart-da04aa7f-493d-44fd-9e6b-06e38c7f8822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729459097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1729459097 |
| Directory | /workspace/15.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3360275246 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 104804725 ps |
| CPU time | 0.93 seconds |
| Started | Jun 09 12:24:38 PM PDT 24 |
| Finished | Jun 09 12:24:40 PM PDT 24 |
| Peak memory | 203732 kb |
| Host | smart-b0049a69-58f0-4237-b3e0-93c6f1fb5486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360275246 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3360275246 |
| Directory | /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.538899966 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 96278871 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:47 PM PDT 24 |
| Finished | Jun 09 12:24:48 PM PDT 24 |
| Peak memory | 203628 kb |
| Host | smart-22a40a02-b724-439e-ad5b-854a9204a569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538899966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.538899966 |
| Directory | /workspace/16.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_intr_test.1018171219 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 44135017 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 12:24:58 PM PDT 24 |
| Finished | Jun 09 12:24:59 PM PDT 24 |
| Peak memory | 203936 kb |
| Host | smart-59a0a6bb-964a-40c7-80ce-9d70a8fbe690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018171219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1018171219 |
| Directory | /workspace/16.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1954122128 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 24052700 ps |
| CPU time | 0.95 seconds |
| Started | Jun 09 12:25:01 PM PDT 24 |
| Finished | Jun 09 12:25:02 PM PDT 24 |
| Peak memory | 203664 kb |
| Host | smart-c81906a1-0a56-4a66-b6b9-5750d7d744ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954122128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.1954122128 |
| Directory | /workspace/16.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.837752183 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1001967665 ps |
| CPU time | 2.44 seconds |
| Started | Jun 09 12:24:44 PM PDT 24 |
| Finished | Jun 09 12:24:46 PM PDT 24 |
| Peak memory | 203884 kb |
| Host | smart-d34bb8df-1437-4146-afc7-90638d3bd9ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837752183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.837752183 |
| Directory | /workspace/16.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2831474931 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 130855661 ps |
| CPU time | 1.01 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203672 kb |
| Host | smart-2527d856-7736-49e7-ba37-a5ca44eed6b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831474931 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2831474931 |
| Directory | /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2606400182 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 19891772 ps |
| CPU time | 0.76 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:36 PM PDT 24 |
| Peak memory | 203660 kb |
| Host | smart-ae0fddcd-b8d7-4d6c-8d32-92c5188ad2e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606400182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2606400182 |
| Directory | /workspace/17.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_intr_test.834974811 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 190532330 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 12:24:40 PM PDT 24 |
| Finished | Jun 09 12:24:41 PM PDT 24 |
| Peak memory | 203536 kb |
| Host | smart-25cd9ead-6540-43d2-840c-31f413b53a81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834974811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.834974811 |
| Directory | /workspace/17.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1420587958 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 37575475 ps |
| CPU time | 0.94 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203564 kb |
| Host | smart-79637474-1810-4e91-bb50-4d9a3f5c17f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420587958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o utstanding.1420587958 |
| Directory | /workspace/17.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1533922336 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 134035349 ps |
| CPU time | 2.77 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:43 PM PDT 24 |
| Peak memory | 203936 kb |
| Host | smart-89683007-41b3-4b84-85cf-83e48348a003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533922336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1533922336 |
| Directory | /workspace/17.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2398280496 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 187486969 ps |
| CPU time | 2.08 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203920 kb |
| Host | smart-c1c2019c-086f-4fd8-82f9-d4854d6c27be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398280496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2398280496 |
| Directory | /workspace/17.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3449263777 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 157641511 ps |
| CPU time | 0.88 seconds |
| Started | Jun 09 12:24:40 PM PDT 24 |
| Finished | Jun 09 12:24:42 PM PDT 24 |
| Peak memory | 203700 kb |
| Host | smart-01a0784d-5ded-40d4-ba75-6403a7556022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449263777 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3449263777 |
| Directory | /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.4086207374 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 18574441 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203636 kb |
| Host | smart-e73464f7-a71e-444f-bbc9-ae500153ff51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086207374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.4086207374 |
| Directory | /workspace/18.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_intr_test.1794421430 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 18496214 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-f4b29e61-7fc5-4109-a5be-d7daaa9d2eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794421430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1794421430 |
| Directory | /workspace/18.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1023694953 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 172404909 ps |
| CPU time | 0.92 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203668 kb |
| Host | smart-0eba6a72-5c06-467d-9e3a-d9aa74f48849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023694953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.1023694953 |
| Directory | /workspace/18.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1993822283 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 153783381 ps |
| CPU time | 1.18 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203860 kb |
| Host | smart-19202056-1214-4954-b13e-1babac03fe96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993822283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1993822283 |
| Directory | /workspace/18.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1290766080 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 624579768 ps |
| CPU time | 1.6 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203904 kb |
| Host | smart-df496b6d-8891-4647-8d89-ff338d2d58ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290766080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1290766080 |
| Directory | /workspace/18.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3612483930 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 82983167 ps |
| CPU time | 1.19 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 219664 kb |
| Host | smart-0aa81089-2e1f-461c-a215-e4d2d3a5594d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612483930 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3612483930 |
| Directory | /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3615791605 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 320462851 ps |
| CPU time | 0.76 seconds |
| Started | Jun 09 12:24:34 PM PDT 24 |
| Finished | Jun 09 12:24:35 PM PDT 24 |
| Peak memory | 203636 kb |
| Host | smart-838ec4ff-8a3f-4e39-8887-1e206cb686c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615791605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3615791605 |
| Directory | /workspace/19.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_intr_test.2108654535 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 20096388 ps |
| CPU time | 0.72 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-ba664efb-c4f4-49b0-aeb1-6d347f71e82e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108654535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2108654535 |
| Directory | /workspace/19.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.671695316 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 75775696 ps |
| CPU time | 1.06 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203840 kb |
| Host | smart-98799bd3-5fb9-4624-9515-1b75bc5eaa2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671695316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou tstanding.671695316 |
| Directory | /workspace/19.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2878979073 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 45771975 ps |
| CPU time | 1.55 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203912 kb |
| Host | smart-f7d49092-d542-47d4-b362-a27d308625f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878979073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2878979073 |
| Directory | /workspace/19.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1578945044 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 401775390 ps |
| CPU time | 2.39 seconds |
| Started | Jun 09 12:24:39 PM PDT 24 |
| Finished | Jun 09 12:24:42 PM PDT 24 |
| Peak memory | 203892 kb |
| Host | smart-9f455cd5-9eaf-44ca-8e15-80907f869dc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578945044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1578945044 |
| Directory | /workspace/19.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2562738493 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 218745603 ps |
| CPU time | 1.39 seconds |
| Started | Jun 09 12:24:23 PM PDT 24 |
| Finished | Jun 09 12:24:25 PM PDT 24 |
| Peak memory | 203828 kb |
| Host | smart-6df40de7-6b37-4949-9ffd-5081626b9db2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562738493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2562738493 |
| Directory | /workspace/2.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1810964789 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 191319215 ps |
| CPU time | 0.71 seconds |
| Started | Jun 09 12:24:14 PM PDT 24 |
| Finished | Jun 09 12:24:15 PM PDT 24 |
| Peak memory | 203552 kb |
| Host | smart-8ad6a9d2-5b1a-4e3a-9f63-88bf5b7415f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810964789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1810964789 |
| Directory | /workspace/2.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2660634360 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 35255098 ps |
| CPU time | 1.46 seconds |
| Started | Jun 09 12:24:17 PM PDT 24 |
| Finished | Jun 09 12:24:19 PM PDT 24 |
| Peak memory | 203968 kb |
| Host | smart-3844a2a6-0a6c-44b3-8c36-b06e9a75a682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660634360 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2660634360 |
| Directory | /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.913210628 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 81242302 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 12:24:16 PM PDT 24 |
| Finished | Jun 09 12:24:17 PM PDT 24 |
| Peak memory | 203656 kb |
| Host | smart-cd4cc0f3-81e1-48e0-8942-166871aacb07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913210628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.913210628 |
| Directory | /workspace/2.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_intr_test.663474550 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 63011462 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 12:24:17 PM PDT 24 |
| Finished | Jun 09 12:24:18 PM PDT 24 |
| Peak memory | 203548 kb |
| Host | smart-5c2bebf0-e747-4a9f-b056-cfeed559f397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663474550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.663474550 |
| Directory | /workspace/2.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2567237496 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 37029665 ps |
| CPU time | 0.9 seconds |
| Started | Jun 09 12:24:18 PM PDT 24 |
| Finished | Jun 09 12:24:19 PM PDT 24 |
| Peak memory | 203660 kb |
| Host | smart-bc03065d-3d3c-43c5-8a02-a829801c1bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567237496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.2567237496 |
| Directory | /workspace/2.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1187010507 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 470271861 ps |
| CPU time | 2.49 seconds |
| Started | Jun 09 12:24:10 PM PDT 24 |
| Finished | Jun 09 12:24:13 PM PDT 24 |
| Peak memory | 203912 kb |
| Host | smart-64e485db-60c7-4a2d-b623-b21b79563ca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187010507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1187010507 |
| Directory | /workspace/2.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1124215672 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 140372178 ps |
| CPU time | 1.48 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:29 PM PDT 24 |
| Peak memory | 203880 kb |
| Host | smart-f1f98538-7349-4745-8908-2c816de5b4ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124215672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1124215672 |
| Directory | /workspace/2.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2193874203 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 43372317 ps |
| CPU time | 0.62 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:36 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-9592507f-adc1-4d8d-b610-dedaa0c81753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193874203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2193874203 |
| Directory | /workspace/20.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.i2c_intr_test.1363322991 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 38579400 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 12:24:40 PM PDT 24 |
| Finished | Jun 09 12:24:42 PM PDT 24 |
| Peak memory | 203592 kb |
| Host | smart-aad5661d-3918-4111-9d8e-81ae437b56b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363322991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1363322991 |
| Directory | /workspace/21.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.i2c_intr_test.3723423231 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 81464622 ps |
| CPU time | 0.61 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-757519c6-3696-4ad4-9537-3a9f89fdde25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723423231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3723423231 |
| Directory | /workspace/22.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.i2c_intr_test.3112075806 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 18524715 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:37 PM PDT 24 |
| Peak memory | 203564 kb |
| Host | smart-2f4c2f59-0dd2-445c-a2bb-20375214476b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112075806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3112075806 |
| Directory | /workspace/23.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.i2c_intr_test.3373675868 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 192002900 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:38 PM PDT 24 |
| Finished | Jun 09 12:24:40 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-e908f389-1acc-43a9-8670-612fe9bc697f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373675868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3373675868 |
| Directory | /workspace/24.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.i2c_intr_test.3451908574 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 54616250 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-53e29027-5dac-4e38-91b0-f65be76deb60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451908574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3451908574 |
| Directory | /workspace/25.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.i2c_intr_test.854264800 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 22191951 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:37 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-e85d8160-5d0e-4b5c-8f35-f5dd6a0414df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854264800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.854264800 |
| Directory | /workspace/26.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.i2c_intr_test.3970073012 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 47633545 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 12:24:35 PM PDT 24 |
| Finished | Jun 09 12:24:36 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-9a8aeded-85ba-4920-9ca7-d07b8e02d728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970073012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3970073012 |
| Directory | /workspace/27.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.i2c_intr_test.1620198658 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 17538107 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:33 PM PDT 24 |
| Finished | Jun 09 12:24:34 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-f0bdd233-4446-4c16-8995-a75a58913dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620198658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1620198658 |
| Directory | /workspace/28.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3144700752 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 112644022 ps |
| CPU time | 1.27 seconds |
| Started | Jun 09 12:24:17 PM PDT 24 |
| Finished | Jun 09 12:24:19 PM PDT 24 |
| Peak memory | 203884 kb |
| Host | smart-e0f32a33-f572-42e0-8545-9eda8fc72c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144700752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3144700752 |
| Directory | /workspace/3.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3462608897 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 83053107 ps |
| CPU time | 0.77 seconds |
| Started | Jun 09 12:24:25 PM PDT 24 |
| Finished | Jun 09 12:24:27 PM PDT 24 |
| Peak memory | 203740 kb |
| Host | smart-767b1205-a664-4de7-a314-12088d0d63d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462608897 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3462608897 |
| Directory | /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3123952810 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 20290500 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 12:24:18 PM PDT 24 |
| Finished | Jun 09 12:24:19 PM PDT 24 |
| Peak memory | 203636 kb |
| Host | smart-67e147f7-74e7-49af-977e-729c23d13906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123952810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3123952810 |
| Directory | /workspace/3.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_intr_test.3408396827 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 37179166 ps |
| CPU time | 0.65 seconds |
| Started | Jun 09 12:24:16 PM PDT 24 |
| Finished | Jun 09 12:24:17 PM PDT 24 |
| Peak memory | 203560 kb |
| Host | smart-c955b8db-16b1-4b12-8a1c-e4a50b6b63fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408396827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3408396827 |
| Directory | /workspace/3.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.988580692 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 375700970 ps |
| CPU time | 2.31 seconds |
| Started | Jun 09 12:24:18 PM PDT 24 |
| Finished | Jun 09 12:24:21 PM PDT 24 |
| Peak memory | 203924 kb |
| Host | smart-ada5b0f5-b43e-46db-87fd-67490e327e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988580692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.988580692 |
| Directory | /workspace/3.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/30.i2c_intr_test.1625222533 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 17435290 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:42 PM PDT 24 |
| Finished | Jun 09 12:24:44 PM PDT 24 |
| Peak memory | 203572 kb |
| Host | smart-c829472f-3b18-4b12-885e-3d42f059cf52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625222533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1625222533 |
| Directory | /workspace/30.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.i2c_intr_test.2855104854 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 49558308 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203532 kb |
| Host | smart-2d37fea1-e118-45f5-8b43-b1a8d80f4545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855104854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2855104854 |
| Directory | /workspace/32.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.i2c_intr_test.2764235099 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 30055332 ps |
| CPU time | 0.71 seconds |
| Started | Jun 09 12:24:33 PM PDT 24 |
| Finished | Jun 09 12:24:35 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-724e74fa-17f2-453f-93a8-44583552313e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764235099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2764235099 |
| Directory | /workspace/33.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.i2c_intr_test.1879880689 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 48200998 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:38 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-9cf34775-6944-467e-ae89-13c072cf02c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879880689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1879880689 |
| Directory | /workspace/34.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.i2c_intr_test.4115348723 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 18365512 ps |
| CPU time | 0.63 seconds |
| Started | Jun 09 12:24:34 PM PDT 24 |
| Finished | Jun 09 12:24:35 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-0da9c537-4eb2-404a-8a53-00123f566d86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115348723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.4115348723 |
| Directory | /workspace/36.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.i2c_intr_test.3270387080 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28564207 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 12:24:37 PM PDT 24 |
| Finished | Jun 09 12:24:39 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-6cbd3020-caff-42ad-bfe4-2ce93deb5480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270387080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3270387080 |
| Directory | /workspace/37.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.i2c_intr_test.4031122303 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 16887785 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 12:24:36 PM PDT 24 |
| Finished | Jun 09 12:24:38 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-ee3d2bcc-a0c9-40db-953c-b8a38de76d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031122303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.4031122303 |
| Directory | /workspace/38.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.987969551 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 606796727 ps |
| CPU time | 2.16 seconds |
| Started | Jun 09 12:24:24 PM PDT 24 |
| Finished | Jun 09 12:24:27 PM PDT 24 |
| Peak memory | 203760 kb |
| Host | smart-2fe07b74-129e-4f85-ae34-ae4aed4651ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987969551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.987969551 |
| Directory | /workspace/4.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3184337855 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 60602985 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 12:24:21 PM PDT 24 |
| Finished | Jun 09 12:24:23 PM PDT 24 |
| Peak memory | 203560 kb |
| Host | smart-e6bb17d5-ddc1-4b26-aede-f1b85e1123ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184337855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3184337855 |
| Directory | /workspace/4.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3277424176 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 47847056 ps |
| CPU time | 0.84 seconds |
| Started | Jun 09 12:24:25 PM PDT 24 |
| Finished | Jun 09 12:24:27 PM PDT 24 |
| Peak memory | 203732 kb |
| Host | smart-3463d4f1-7085-43dd-b876-60e3d021d10d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277424176 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3277424176 |
| Directory | /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1636610998 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 46621608 ps |
| CPU time | 0.77 seconds |
| Started | Jun 09 12:24:17 PM PDT 24 |
| Finished | Jun 09 12:24:18 PM PDT 24 |
| Peak memory | 203652 kb |
| Host | smart-fedf2753-6165-4a20-8f4e-ba4145981960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636610998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1636610998 |
| Directory | /workspace/4.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_intr_test.3503064662 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 56762154 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 12:24:17 PM PDT 24 |
| Finished | Jun 09 12:24:18 PM PDT 24 |
| Peak memory | 203552 kb |
| Host | smart-babd162a-d837-4e37-9b58-1af2471bb224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503064662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3503064662 |
| Directory | /workspace/4.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.769822988 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 146208999 ps |
| CPU time | 0.9 seconds |
| Started | Jun 09 12:24:14 PM PDT 24 |
| Finished | Jun 09 12:24:16 PM PDT 24 |
| Peak memory | 203628 kb |
| Host | smart-35fd8749-2a82-46cf-93b7-ecddfc5f97a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769822988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out standing.769822988 |
| Directory | /workspace/4.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.4104803471 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 353525083 ps |
| CPU time | 2.02 seconds |
| Started | Jun 09 12:24:20 PM PDT 24 |
| Finished | Jun 09 12:24:22 PM PDT 24 |
| Peak memory | 203896 kb |
| Host | smart-ec9edbf7-5f1f-4e7a-9f5d-4a5ae91ecce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104803471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.4104803471 |
| Directory | /workspace/4.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2863460776 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 282521377 ps |
| CPU time | 2.34 seconds |
| Started | Jun 09 12:24:19 PM PDT 24 |
| Finished | Jun 09 12:24:22 PM PDT 24 |
| Peak memory | 203832 kb |
| Host | smart-26cd3253-d54a-40c5-bc08-bd4c19a23b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863460776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2863460776 |
| Directory | /workspace/4.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.i2c_intr_test.1562333065 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 33626790 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 12:24:42 PM PDT 24 |
| Finished | Jun 09 12:24:43 PM PDT 24 |
| Peak memory | 203588 kb |
| Host | smart-1606602b-dba4-44a7-8fdf-3b11d6a26ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562333065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1562333065 |
| Directory | /workspace/40.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.i2c_intr_test.2327038533 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 23829241 ps |
| CPU time | 0.65 seconds |
| Started | Jun 09 12:24:41 PM PDT 24 |
| Finished | Jun 09 12:24:42 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-0e1e3c38-141d-4343-8f24-1fa9e349d9d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327038533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2327038533 |
| Directory | /workspace/41.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.i2c_intr_test.3692669157 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 18452449 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 12:24:46 PM PDT 24 |
| Finished | Jun 09 12:24:47 PM PDT 24 |
| Peak memory | 203540 kb |
| Host | smart-a08fa303-2d63-450c-8cfa-333691845456 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692669157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3692669157 |
| Directory | /workspace/42.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.i2c_intr_test.574774911 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 200245530 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 12:24:40 PM PDT 24 |
| Finished | Jun 09 12:24:41 PM PDT 24 |
| Peak memory | 203548 kb |
| Host | smart-57ecaeaa-d15f-466b-abcc-00a0d1e83e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574774911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.574774911 |
| Directory | /workspace/43.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.i2c_intr_test.2821892558 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 50820707 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 12:24:43 PM PDT 24 |
| Finished | Jun 09 12:24:50 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-5ca1687d-2e58-4363-a0de-ddbaec1490d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821892558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2821892558 |
| Directory | /workspace/44.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.i2c_intr_test.1521537949 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 32031656 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:41 PM PDT 24 |
| Finished | Jun 09 12:24:42 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-345f87ae-095f-4dd0-84d4-f551e13a34f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521537949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1521537949 |
| Directory | /workspace/45.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.i2c_intr_test.2727478490 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 46767343 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:25:01 PM PDT 24 |
| Finished | Jun 09 12:25:02 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-ea2fcebf-78a0-41da-b710-933c303f2a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727478490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2727478490 |
| Directory | /workspace/46.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.i2c_intr_test.3744238029 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 18108652 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 12:24:52 PM PDT 24 |
| Finished | Jun 09 12:24:53 PM PDT 24 |
| Peak memory | 203536 kb |
| Host | smart-76de7322-d9aa-4ff8-b685-c258ce8070f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744238029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3744238029 |
| Directory | /workspace/48.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.i2c_intr_test.2662748075 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 21349053 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 12:24:43 PM PDT 24 |
| Finished | Jun 09 12:24:44 PM PDT 24 |
| Peak memory | 203548 kb |
| Host | smart-c741a278-d691-42e4-ba5f-1f0f2d8e3409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662748075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2662748075 |
| Directory | /workspace/49.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.823466553 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 20102090 ps |
| CPU time | 0.82 seconds |
| Started | Jun 09 12:24:22 PM PDT 24 |
| Finished | Jun 09 12:24:24 PM PDT 24 |
| Peak memory | 203704 kb |
| Host | smart-fb0d9d22-55d3-49d9-88bf-1b2073b23b4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823466553 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.823466553 |
| Directory | /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3666408454 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 22435496 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 12:24:25 PM PDT 24 |
| Finished | Jun 09 12:24:27 PM PDT 24 |
| Peak memory | 203540 kb |
| Host | smart-f32b7276-0978-4382-a552-df2bda6a51cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666408454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3666408454 |
| Directory | /workspace/5.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_intr_test.266804408 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 16567791 ps |
| CPU time | 0.62 seconds |
| Started | Jun 09 12:24:17 PM PDT 24 |
| Finished | Jun 09 12:24:18 PM PDT 24 |
| Peak memory | 203556 kb |
| Host | smart-6c31c560-db25-40ba-8e87-3e7abb281b5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266804408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.266804408 |
| Directory | /workspace/5.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1371924905 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 19788305 ps |
| CPU time | 0.88 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:28 PM PDT 24 |
| Peak memory | 203612 kb |
| Host | smart-728ac7ed-f4f1-4397-a502-907fe92861c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371924905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.1371924905 |
| Directory | /workspace/5.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3076715335 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 113784761 ps |
| CPU time | 2.6 seconds |
| Started | Jun 09 12:24:18 PM PDT 24 |
| Finished | Jun 09 12:24:21 PM PDT 24 |
| Peak memory | 203928 kb |
| Host | smart-41689d78-f7ee-4658-a6ea-9d9ad21b3778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076715335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3076715335 |
| Directory | /workspace/5.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1256382970 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 85131051 ps |
| CPU time | 2.26 seconds |
| Started | Jun 09 12:24:15 PM PDT 24 |
| Finished | Jun 09 12:24:18 PM PDT 24 |
| Peak memory | 203908 kb |
| Host | smart-2fd5a07a-69d9-4349-aa72-9b20d2bcc327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256382970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1256382970 |
| Directory | /workspace/5.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4233456744 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 27102617 ps |
| CPU time | 1.11 seconds |
| Started | Jun 09 12:24:22 PM PDT 24 |
| Finished | Jun 09 12:24:23 PM PDT 24 |
| Peak memory | 203944 kb |
| Host | smart-6c962307-0123-4db1-99bf-a484b2b26b49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233456744 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.4233456744 |
| Directory | /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3838977700 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 20272491 ps |
| CPU time | 0.75 seconds |
| Started | Jun 09 12:24:21 PM PDT 24 |
| Finished | Jun 09 12:24:22 PM PDT 24 |
| Peak memory | 203640 kb |
| Host | smart-6d46f60c-f0ba-41f1-8c78-6e37b6fa8ea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838977700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3838977700 |
| Directory | /workspace/6.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_intr_test.2877012298 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 57412830 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 12:24:23 PM PDT 24 |
| Finished | Jun 09 12:24:24 PM PDT 24 |
| Peak memory | 203484 kb |
| Host | smart-62e35b32-1e97-4457-b453-966e7f401950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877012298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2877012298 |
| Directory | /workspace/6.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3810650030 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 60861236 ps |
| CPU time | 0.87 seconds |
| Started | Jun 09 12:24:20 PM PDT 24 |
| Finished | Jun 09 12:24:22 PM PDT 24 |
| Peak memory | 203576 kb |
| Host | smart-403466c5-bb4c-44f5-9998-34a377fb205e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810650030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.3810650030 |
| Directory | /workspace/6.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1569023733 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 26495525 ps |
| CPU time | 0.9 seconds |
| Started | Jun 09 12:24:22 PM PDT 24 |
| Finished | Jun 09 12:24:23 PM PDT 24 |
| Peak memory | 203708 kb |
| Host | smart-9b0ff277-52cf-48dd-ac70-b78546a4747f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569023733 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1569023733 |
| Directory | /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2189384990 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 68360582 ps |
| CPU time | 0.72 seconds |
| Started | Jun 09 12:24:23 PM PDT 24 |
| Finished | Jun 09 12:24:24 PM PDT 24 |
| Peak memory | 203576 kb |
| Host | smart-3395cf80-e27c-456c-94e1-c85d1568e21d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189384990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2189384990 |
| Directory | /workspace/7.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_intr_test.3154334698 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 15419282 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 12:24:22 PM PDT 24 |
| Finished | Jun 09 12:24:23 PM PDT 24 |
| Peak memory | 203556 kb |
| Host | smart-3a0d7e74-183f-4967-9a8c-1d59e867e2ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154334698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3154334698 |
| Directory | /workspace/7.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2552251326 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 29982840 ps |
| CPU time | 0.89 seconds |
| Started | Jun 09 12:24:23 PM PDT 24 |
| Finished | Jun 09 12:24:24 PM PDT 24 |
| Peak memory | 203592 kb |
| Host | smart-ac8837d1-d4fb-4fdf-bba6-4172ac873c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552251326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.2552251326 |
| Directory | /workspace/7.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2568963560 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 66396318 ps |
| CPU time | 1.8 seconds |
| Started | Jun 09 12:24:23 PM PDT 24 |
| Finished | Jun 09 12:24:26 PM PDT 24 |
| Peak memory | 203944 kb |
| Host | smart-907fa0c1-6e74-4ee0-9efd-fbd081b37117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568963560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2568963560 |
| Directory | /workspace/7.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.596369012 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 160291816 ps |
| CPU time | 2.44 seconds |
| Started | Jun 09 12:24:31 PM PDT 24 |
| Finished | Jun 09 12:24:34 PM PDT 24 |
| Peak memory | 203804 kb |
| Host | smart-1e06d62c-4546-4dfb-8470-5de215f07547 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596369012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.596369012 |
| Directory | /workspace/7.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2161978020 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 30729883 ps |
| CPU time | 1.12 seconds |
| Started | Jun 09 12:24:19 PM PDT 24 |
| Finished | Jun 09 12:24:21 PM PDT 24 |
| Peak memory | 203976 kb |
| Host | smart-d6ba0a6c-f351-412a-af89-0a1f57b000f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161978020 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2161978020 |
| Directory | /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3277390722 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 87749803 ps |
| CPU time | 0.91 seconds |
| Started | Jun 09 12:24:21 PM PDT 24 |
| Finished | Jun 09 12:24:22 PM PDT 24 |
| Peak memory | 203684 kb |
| Host | smart-6fc59933-1d15-40df-9ab7-ba51df25ce55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277390722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3277390722 |
| Directory | /workspace/8.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_intr_test.2694649510 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 19391012 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:28 PM PDT 24 |
| Peak memory | 203540 kb |
| Host | smart-6abec0f2-a3e4-4fae-8078-bc2fae537476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694649510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2694649510 |
| Directory | /workspace/8.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.860999655 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 64474916 ps |
| CPU time | 1.3 seconds |
| Started | Jun 09 12:24:23 PM PDT 24 |
| Finished | Jun 09 12:24:25 PM PDT 24 |
| Peak memory | 203804 kb |
| Host | smart-41d5a595-2f1b-4544-98c1-167586279710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860999655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out standing.860999655 |
| Directory | /workspace/8.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1880114247 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 195383411 ps |
| CPU time | 1.21 seconds |
| Started | Jun 09 12:24:29 PM PDT 24 |
| Finished | Jun 09 12:24:30 PM PDT 24 |
| Peak memory | 203832 kb |
| Host | smart-69b7a737-444e-4ba1-a887-b73200d46c5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880114247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1880114247 |
| Directory | /workspace/8.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3497451535 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 612934872 ps |
| CPU time | 2.38 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:31 PM PDT 24 |
| Peak memory | 203868 kb |
| Host | smart-5428e6c6-5816-4230-ba22-bb320897172f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497451535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3497451535 |
| Directory | /workspace/8.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3210450861 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 273988190 ps |
| CPU time | 0.88 seconds |
| Started | Jun 09 12:24:25 PM PDT 24 |
| Finished | Jun 09 12:24:27 PM PDT 24 |
| Peak memory | 204048 kb |
| Host | smart-1a6d88bb-76f0-4db6-b032-3ccd8a2c3fe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210450861 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3210450861 |
| Directory | /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1229419311 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 42348409 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 12:24:22 PM PDT 24 |
| Finished | Jun 09 12:24:23 PM PDT 24 |
| Peak memory | 203568 kb |
| Host | smart-4e62579e-dcd1-404a-9bfb-76ec34a9d820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229419311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1229419311 |
| Directory | /workspace/9.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_intr_test.2188781410 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 24040708 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 12:24:25 PM PDT 24 |
| Finished | Jun 09 12:24:27 PM PDT 24 |
| Peak memory | 203512 kb |
| Host | smart-cabc87c0-236e-49c7-b266-84ef2c4a901f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188781410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2188781410 |
| Directory | /workspace/9.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1481566200 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 166983802 ps |
| CPU time | 0.87 seconds |
| Started | Jun 09 12:24:27 PM PDT 24 |
| Finished | Jun 09 12:24:28 PM PDT 24 |
| Peak memory | 203664 kb |
| Host | smart-70d5a0bc-c642-42b9-bbb5-4ca4dce83a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481566200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.1481566200 |
| Directory | /workspace/9.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4095202031 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 912769115 ps |
| CPU time | 2 seconds |
| Started | Jun 09 12:24:23 PM PDT 24 |
| Finished | Jun 09 12:24:26 PM PDT 24 |
| Peak memory | 203832 kb |
| Host | smart-e22b406c-cd3a-45ab-9820-128d53995af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095202031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.4095202031 |
| Directory | /workspace/9.i2c_tl_errors/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |