Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_reset_cg

Group : i2c_env_pkg::i2c_fifo_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_fifo_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	20	0	0.00
Crosses	24	24	0	0.00

Variables for Group i2c_env_pkg::i2c_fifo_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_overflow	2	2	0	0.00	100	1	1	2
cp_acq_threshold	2	2	0	0.00	100	1	1	2
cp_acqrst	2	2	0	0.00	100	1	1	2
cp_fmt_threshold	2	2	0	0.00	100	1	1	2
cp_fmtrst	2	2	0	0.00	100	1	1	2
cp_rx_overflow	2	2	0	0.00	100	1	1	2
cp_rx_threshold	2	2	0	0.00	100	1	1	2
cp_rxrst	2	2	0	0.00	100	1	1	2
cp_tx_threshold	2	2	0	0.00	100	1	1	2
cp_txrst	2	2	0	0.00	100	1	1	2

Crosses for Group i2c_env_pkg::i2c_fifo_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fmt_threshold_cross	4	4	0	0.00	100	1	1	0
cp_rx_threshold_cross	4	4	0	0.00	100	1	1	0
cp_acq_threshold_cross	4	4	0	0.00	100	1	1	0
cp_rx_overflow_cross	4	4	0	0.00	100	1	1	0
cp_acq_overflow_cross	4	4	0	0.00	100	1	1	0
cp_tx_threshold_cross	4	4	0	0.00	100	1	1	0

Summary for Variable cp_acq_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_acq_overflow

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_acq_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_acq_threshold

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_acqrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_acqrst

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_fmt_threshold

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_fmtrst

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_rx_overflow

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_rx_threshold

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_rxrst

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_tx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_tx_threshold

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_txrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_txrst

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross cp_fmt_threshold_cross

Samples crossed: cp_fmt_threshold cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for cp_fmt_threshold_cross

Uncovered bins

cp_fmt_threshold	cp_fmtrst	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross cp_rx_threshold_cross

Samples crossed: cp_rx_threshold cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for cp_rx_threshold_cross

Uncovered bins

cp_rx_threshold	cp_rxrst	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross cp_acq_threshold_cross

Samples crossed: cp_acq_threshold cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for cp_acq_threshold_cross

Uncovered bins

cp_acq_threshold	cp_fmtrst	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross cp_rx_overflow_cross

Samples crossed: cp_rx_overflow cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for cp_rx_overflow_cross

Uncovered bins

cp_rx_overflow	cp_rxrst	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross cp_acq_overflow_cross

Samples crossed: cp_acq_overflow cp_acqrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for cp_acq_overflow_cross

Uncovered bins

cp_acq_overflow	cp_acqrst	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross cp_tx_threshold_cross

Samples crossed: cp_tx_threshold cp_txrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for cp_tx_threshold_cross

Uncovered bins

cp_tx_threshold	cp_txrst	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4