Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
15 |
0 |
15 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[1] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[2] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[3] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[4] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[5] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[6] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[7] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[8] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[9] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[10] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[11] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[12] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[13] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
all_pins[14] |
333 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T6 |
1 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
4125 |
1 |
|
|
T1 |
15 |
|
T3 |
87 |
|
T6 |
15 |
values[0x1] |
870 |
1 |
|
|
T3 |
33 |
|
T8 |
13 |
|
T12 |
27 |
transitions[0x0=>0x1] |
651 |
1 |
|
|
T3 |
22 |
|
T8 |
11 |
|
T12 |
19 |
transitions[0x1=>0x0] |
659 |
1 |
|
|
T3 |
22 |
|
T8 |
11 |
|
T12 |
19 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
60 |
0 |
60 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
270 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T6 |
1 |
all_pins[0] |
values[0x1] |
63 |
1 |
|
|
T3 |
3 |
|
T8 |
1 |
|
T12 |
1 |
all_pins[0] |
transitions[0x0=>0x1] |
51 |
1 |
|
|
T3 |
3 |
|
T8 |
1 |
|
T12 |
1 |
all_pins[0] |
transitions[0x1=>0x0] |
34 |
1 |
|
|
T3 |
2 |
|
T12 |
2 |
|
T13 |
1 |
all_pins[1] |
values[0x0] |
287 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T6 |
1 |
all_pins[1] |
values[0x1] |
46 |
1 |
|
|
T3 |
2 |
|
T12 |
2 |
|
T13 |
1 |
all_pins[1] |
transitions[0x0=>0x1] |
34 |
1 |
|
|
T3 |
2 |
|
T12 |
2 |
|
T44 |
2 |
all_pins[1] |
transitions[0x1=>0x0] |
47 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T14 |
1 |
all_pins[2] |
values[0x0] |
274 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T6 |
1 |
all_pins[2] |
values[0x1] |
59 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T13 |
1 |
all_pins[2] |
transitions[0x0=>0x1] |
46 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T13 |
1 |
all_pins[2] |
transitions[0x1=>0x0] |
58 |
1 |
|
|
T3 |
2 |
|
T8 |
2 |
|
T12 |
5 |
all_pins[3] |
values[0x0] |
262 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T6 |
1 |
all_pins[3] |
values[0x1] |
71 |
1 |
|
|
T3 |
2 |
|
T8 |
2 |
|
T12 |
5 |
all_pins[3] |
transitions[0x0=>0x1] |
57 |
1 |
|
|
T3 |
1 |
|
T8 |
1 |
|
T12 |
5 |
all_pins[3] |
transitions[0x1=>0x0] |
34 |
1 |
|
|
T12 |
1 |
|
T13 |
1 |
|
T14 |
1 |
all_pins[4] |
values[0x0] |
285 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T6 |
1 |
all_pins[4] |
values[0x1] |
48 |
1 |
|
|
T3 |
1 |
|
T8 |
1 |
|
T12 |
1 |
all_pins[4] |
transitions[0x0=>0x1] |
38 |
1 |
|
|
T8 |
1 |
|
T12 |
1 |
|
T13 |
1 |
all_pins[4] |
transitions[0x1=>0x0] |
49 |
1 |
|
|
T3 |
2 |
|
T8 |
2 |
|
T14 |
1 |
all_pins[5] |
values[0x0] |
274 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T6 |
1 |
all_pins[5] |
values[0x1] |
59 |
1 |
|
|
T3 |
3 |
|
T8 |
2 |
|
T14 |
1 |
all_pins[5] |
transitions[0x0=>0x1] |
44 |
1 |
|
|
T3 |
3 |
|
T8 |
2 |
|
T14 |
1 |
all_pins[5] |
transitions[0x1=>0x0] |
44 |
1 |
|
|
T3 |
2 |
|
T12 |
1 |
|
T13 |
2 |
all_pins[6] |
values[0x0] |
274 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T6 |
1 |
all_pins[6] |
values[0x1] |
59 |
1 |
|
|
T3 |
2 |
|
T12 |
1 |
|
T13 |
2 |
all_pins[6] |
transitions[0x0=>0x1] |
43 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T13 |
2 |
all_pins[6] |
transitions[0x1=>0x0] |
41 |
1 |
|
|
T3 |
1 |
|
T12 |
2 |
|
T15 |
3 |
all_pins[7] |
values[0x0] |
276 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T6 |
1 |
all_pins[7] |
values[0x1] |
57 |
1 |
|
|
T3 |
2 |
|
T12 |
2 |
|
T15 |
3 |
all_pins[7] |
transitions[0x0=>0x1] |
42 |
1 |
|
|
T3 |
1 |
|
T15 |
3 |
|
T38 |
5 |
all_pins[7] |
transitions[0x1=>0x0] |
34 |
1 |
|
|
T3 |
2 |
|
T12 |
1 |
|
T13 |
1 |
all_pins[8] |
values[0x0] |
284 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T6 |
1 |
all_pins[8] |
values[0x1] |
49 |
1 |
|
|
T3 |
3 |
|
T12 |
3 |
|
T13 |
1 |
all_pins[8] |
transitions[0x0=>0x1] |
37 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T13 |
1 |
all_pins[8] |
transitions[0x1=>0x0] |
43 |
1 |
|
|
T3 |
1 |
|
T8 |
3 |
|
T14 |
1 |
all_pins[9] |
values[0x0] |
278 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T6 |
1 |
all_pins[9] |
values[0x1] |
55 |
1 |
|
|
T3 |
3 |
|
T8 |
3 |
|
T12 |
2 |
all_pins[9] |
transitions[0x0=>0x1] |
39 |
1 |
|
|
T3 |
2 |
|
T8 |
2 |
|
T12 |
1 |
all_pins[9] |
transitions[0x1=>0x0] |
46 |
1 |
|
|
T8 |
1 |
|
T14 |
1 |
|
T15 |
2 |
all_pins[10] |
values[0x0] |
271 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T6 |
1 |
all_pins[10] |
values[0x1] |
62 |
1 |
|
|
T3 |
1 |
|
T8 |
2 |
|
T12 |
1 |
all_pins[10] |
transitions[0x0=>0x1] |
46 |
1 |
|
|
T3 |
1 |
|
T8 |
2 |
|
T14 |
2 |
all_pins[10] |
transitions[0x1=>0x0] |
33 |
1 |
|
|
T3 |
2 |
|
T8 |
1 |
|
T12 |
1 |
all_pins[11] |
values[0x0] |
284 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T6 |
1 |
all_pins[11] |
values[0x1] |
49 |
1 |
|
|
T3 |
2 |
|
T8 |
1 |
|
T12 |
2 |
all_pins[11] |
transitions[0x0=>0x1] |
38 |
1 |
|
|
T3 |
1 |
|
T8 |
1 |
|
T38 |
2 |
all_pins[11] |
transitions[0x1=>0x0] |
48 |
1 |
|
|
T3 |
2 |
|
T8 |
1 |
|
T12 |
1 |
all_pins[12] |
values[0x0] |
274 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T6 |
1 |
all_pins[12] |
values[0x1] |
59 |
1 |
|
|
T3 |
3 |
|
T8 |
1 |
|
T12 |
3 |
all_pins[12] |
transitions[0x0=>0x1] |
46 |
1 |
|
|
T3 |
2 |
|
T8 |
1 |
|
T12 |
3 |
all_pins[12] |
transitions[0x1=>0x0] |
60 |
1 |
|
|
T3 |
1 |
|
T12 |
2 |
|
T13 |
2 |
all_pins[13] |
values[0x0] |
260 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T6 |
1 |
all_pins[13] |
values[0x1] |
73 |
1 |
|
|
T3 |
2 |
|
T12 |
2 |
|
T13 |
2 |
all_pins[13] |
transitions[0x0=>0x1] |
54 |
1 |
|
|
T3 |
1 |
|
T12 |
2 |
|
T15 |
2 |
all_pins[13] |
transitions[0x1=>0x0] |
42 |
1 |
|
|
T3 |
2 |
|
T12 |
1 |
|
T14 |
1 |
all_pins[14] |
values[0x0] |
272 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T6 |
1 |
all_pins[14] |
values[0x1] |
61 |
1 |
|
|
T3 |
3 |
|
T12 |
1 |
|
T13 |
2 |
all_pins[14] |
transitions[0x0=>0x1] |
36 |
1 |
|
|
T3 |
2 |
|
T12 |
1 |
|
T13 |
2 |
all_pins[14] |
transitions[0x1=>0x0] |
46 |
1 |
|
|
T3 |
2 |
|
T8 |
1 |
|
T12 |
1 |