Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T3	7		T8	4		T12	7
all_values[1]	263	1			T3	7		T8	4		T12	7
all_values[2]	263	1			T3	7		T8	4		T12	7
all_values[3]	263	1			T3	7		T8	4		T12	7
all_values[4]	263	1			T3	7		T8	4		T12	7
all_values[5]	263	1			T3	7		T8	4		T12	7
all_values[6]	263	1			T3	7		T8	4		T12	7
all_values[7]	263	1			T3	7		T8	4		T12	7
all_values[8]	263	1			T3	7		T8	4		T12	7
all_values[9]	263	1			T3	7		T8	4		T12	7
all_values[10]	263	1			T3	7		T8	4		T12	7
all_values[11]	263	1			T3	7		T8	4		T12	7
all_values[12]	263	1			T3	7		T8	4		T12	7
all_values[13]	263	1			T3	7		T8	4		T12	7
all_values[14]	263	1			T3	7		T8	4		T12	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2164

1

T3

54

T8

30

T12

65

auto[1]

1781

1

T3

51

T8

30

T12

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

755

1

T3

12

T8

10

T12

14

auto[1]

3190

1

T3

93

T8

50

T12

91

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T3

63

T8

34

T12

57

auto[1]

1599

1

T3

42

T8

26

T12

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T3	2		T12	2		T13	1
all_values[0]	auto[0]	auto[0]	auto[1]	44	1			T3	1		T12	1		T13	1
all_values[0]	auto[0]	auto[1]	auto[0]	25	1			T8	2		T43	1		T39	1
all_values[0]	auto[0]	auto[1]	auto[1]	51	1			T3	1		T8	1		T12	2
all_values[0]	auto[1]	auto[0]	auto[1]	60	1			T3	1		T12	1		T13	2
all_values[0]	auto[1]	auto[1]	auto[1]	49	1			T3	2		T8	1		T12	1
all_values[1]	auto[0]	auto[0]	auto[0]	27	1			T3	1		T12	1		T13	1
all_values[1]	auto[0]	auto[0]	auto[1]	54	1			T8	2		T12	2		T14	1
all_values[1]	auto[0]	auto[1]	auto[0]	14	1			T13	1		T43	2		T67	1
all_values[1]	auto[0]	auto[1]	auto[1]	64	1			T3	3		T12	2		T13	1
all_values[1]	auto[1]	auto[0]	auto[1]	66	1			T3	1		T8	2		T14	1
all_values[1]	auto[1]	auto[1]	auto[1]	38	1			T3	2		T12	2		T13	1
all_values[2]	auto[0]	auto[0]	auto[0]	21	1			T12	1		T13	1		T38	5
all_values[2]	auto[0]	auto[0]	auto[1]	51	1			T3	4		T12	3		T15	1
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T8	4		T13	1		T43	4
all_values[2]	auto[0]	auto[1]	auto[1]	58	1			T3	2		T13	1		T14	1
all_values[2]	auto[1]	auto[0]	auto[1]	65	1			T3	1		T12	3		T14	3
all_values[2]	auto[1]	auto[1]	auto[1]	44	1			T13	1		T15	1		T44	1
all_values[3]	auto[0]	auto[0]	auto[0]	37	1			T3	1		T15	1		T43	2
all_values[3]	auto[0]	auto[0]	auto[1]	49	1			T3	3		T8	2		T12	1
all_values[3]	auto[0]	auto[1]	auto[0]	17	1			T43	2		T39	1		T67	1
all_values[3]	auto[0]	auto[1]	auto[1]	53	1			T3	2		T8	1		T12	1
all_values[3]	auto[1]	auto[0]	auto[1]	54	1			T12	2		T13	1		T15	1
all_values[3]	auto[1]	auto[1]	auto[1]	53	1			T3	1		T8	1		T12	3
all_values[4]	auto[0]	auto[0]	auto[0]	37	1			T3	1		T12	1		T13	2
all_values[4]	auto[0]	auto[0]	auto[1]	52	1			T3	1		T8	2		T12	3
all_values[4]	auto[0]	auto[1]	auto[0]	10	1			T43	2		T68	1		T69	1
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T3	4		T8	1		T12	1
all_values[4]	auto[1]	auto[0]	auto[1]	50	1			T12	1		T15	1		T38	2
all_values[4]	auto[1]	auto[1]	auto[1]	48	1			T3	1		T8	1		T12	1
all_values[5]	auto[0]	auto[0]	auto[0]	34	1			T12	1		T14	1		T15	1
all_values[5]	auto[0]	auto[0]	auto[1]	53	1			T12	1		T13	2		T14	1
all_values[5]	auto[0]	auto[1]	auto[0]	24	1			T12	3		T38	4		T70	1
all_values[5]	auto[0]	auto[1]	auto[1]	55	1			T3	4		T8	2		T43	2
all_values[5]	auto[1]	auto[0]	auto[1]	52	1			T3	2		T12	2		T13	2
all_values[5]	auto[1]	auto[1]	auto[1]	45	1			T3	1		T8	2		T14	2
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T3	1		T8	2		T43	2
all_values[6]	auto[0]	auto[0]	auto[1]	49	1			T8	1		T12	2		T13	2
all_values[6]	auto[0]	auto[1]	auto[0]	13	1			T3	1		T44	3		T70	2
all_values[6]	auto[0]	auto[1]	auto[1]	48	1			T3	2		T12	1		T13	1
all_values[6]	auto[1]	auto[0]	auto[1]	65	1			T3	2		T8	1		T12	3
all_values[6]	auto[1]	auto[1]	auto[1]	47	1			T3	1		T12	1		T13	1
all_values[7]	auto[0]	auto[0]	auto[0]	31	1			T8	1		T13	1		T71	2
all_values[7]	auto[0]	auto[0]	auto[1]	52	1			T3	1		T12	3		T14	2
all_values[7]	auto[0]	auto[1]	auto[0]	19	1			T13	3		T44	1		T72	1
all_values[7]	auto[0]	auto[1]	auto[1]	56	1			T3	2		T8	2		T12	1
all_values[7]	auto[1]	auto[0]	auto[1]	60	1			T3	2		T8	1		T12	1
all_values[7]	auto[1]	auto[1]	auto[1]	45	1			T3	2		T12	2		T15	2
all_values[8]	auto[0]	auto[0]	auto[0]	29	1			T13	1		T15	1		T43	2
all_values[8]	auto[0]	auto[0]	auto[1]	66	1			T3	3		T8	1		T12	1
all_values[8]	auto[0]	auto[1]	auto[0]	23	1			T15	4		T43	2		T44	1
all_values[8]	auto[0]	auto[1]	auto[1]	50	1			T3	1		T12	1		T13	2
all_values[8]	auto[1]	auto[0]	auto[1]	57	1			T3	1		T8	3		T12	4
all_values[8]	auto[1]	auto[1]	auto[1]	38	1			T3	2		T12	1		T13	1
all_values[9]	auto[0]	auto[0]	auto[0]	37	1			T43	2		T44	2		T38	1
all_values[9]	auto[0]	auto[0]	auto[1]	58	1			T3	2		T12	2		T13	1
all_values[9]	auto[0]	auto[1]	auto[0]	17	1			T43	2		T44	2		T73	2
all_values[9]	auto[0]	auto[1]	auto[1]	40	1			T3	1		T8	1		T12	1
all_values[9]	auto[1]	auto[0]	auto[1]	62	1			T3	4		T12	3		T13	3
all_values[9]	auto[1]	auto[1]	auto[1]	49	1			T8	3		T12	1		T14	2
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T3	2		T12	1		T13	2
all_values[10]	auto[0]	auto[0]	auto[1]	41	1			T3	2		T12	4		T13	1
all_values[10]	auto[0]	auto[1]	auto[0]	19	1			T8	1		T38	2		T70	1
all_values[10]	auto[0]	auto[1]	auto[1]	58	1			T3	1		T8	1		T14	1
all_values[10]	auto[1]	auto[0]	auto[1]	56	1			T3	2		T12	1		T13	1
all_values[10]	auto[1]	auto[1]	auto[1]	51	1			T8	2		T12	1		T14	2
all_values[11]	auto[0]	auto[0]	auto[0]	25	1			T14	3		T43	1		T38	1
all_values[11]	auto[0]	auto[0]	auto[1]	61	1			T3	1		T8	1		T13	1
all_values[11]	auto[0]	auto[1]	auto[0]	18	1			T13	2		T14	1		T68	3
all_values[11]	auto[0]	auto[1]	auto[1]	47	1			T3	3		T8	1		T12	3
all_values[11]	auto[1]	auto[0]	auto[1]	60	1			T3	1		T8	1		T12	1
all_values[11]	auto[1]	auto[1]	auto[1]	52	1			T3	2		T8	1		T12	3
all_values[12]	auto[0]	auto[0]	auto[0]	44	1			T3	1		T12	1		T13	1
all_values[12]	auto[0]	auto[0]	auto[1]	43	1			T12	2		T43	2		T44	2
all_values[12]	auto[0]	auto[1]	auto[0]	18	1			T13	3		T15	1		T38	1
all_values[12]	auto[0]	auto[1]	auto[1]	51	1			T3	2		T8	1		T14	2
all_values[12]	auto[1]	auto[0]	auto[1]	54	1			T3	1		T8	2		T12	1
all_values[12]	auto[1]	auto[1]	auto[1]	53	1			T3	3		T8	1		T12	3
all_values[13]	auto[0]	auto[0]	auto[0]	31	1			T3	2		T12	1		T13	1
all_values[13]	auto[0]	auto[0]	auto[1]	48	1			T8	1		T12	2		T14	2
all_values[13]	auto[0]	auto[1]	auto[0]	9	1			T13	1		T74	1		T75	1
all_values[13]	auto[0]	auto[1]	auto[1]	61	1			T3	2		T12	1		T13	1
all_values[13]	auto[1]	auto[0]	auto[1]	68	1			T3	1		T8	3		T12	3
all_values[13]	auto[1]	auto[1]	auto[1]	46	1			T3	2		T13	1		T15	1
all_values[14]	auto[0]	auto[0]	auto[0]	21	1			T12	1		T15	1		T74	2
all_values[14]	auto[0]	auto[0]	auto[1]	63	1			T3	2		T8	3		T12	1
all_values[14]	auto[0]	auto[1]	auto[0]	18	1			T12	1		T14	1		T76	1
all_values[14]	auto[0]	auto[1]	auto[1]	49	1			T3	1		T12	1		T13	2
all_values[14]	auto[1]	auto[0]	auto[1]	64	1			T3	4		T8	1		T12	1
all_values[14]	auto[1]	auto[1]	auto[1]	48	1			T12	2		T13	1		T14	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal