Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	838497	1			T1	2		T2	3		T3	3
all_values[1]	838497	1			T1	2		T2	3		T3	3
all_values[2]	838497	1			T1	2		T2	3		T3	3
all_values[3]	838497	1			T1	2		T2	3		T3	3
all_values[4]	838497	1			T1	2		T2	3		T3	3
all_values[5]	838497	1			T1	2		T2	3		T3	3
all_values[6]	838497	1			T1	2		T2	3		T3	3
all_values[7]	838497	1			T1	2		T2	3		T3	3
all_values[8]	838497	1			T1	2		T2	3		T3	3
all_values[9]	838497	1			T1	2		T2	3		T3	3
all_values[10]	838497	1			T1	2		T2	3		T3	3
all_values[11]	838497	1			T1	2		T2	3		T3	3
all_values[12]	838497	1			T1	2		T2	3		T3	3
all_values[13]	838497	1			T1	2		T2	3		T3	3
all_values[14]	838497	1			T1	2		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10326473

1

T1

26

T2

38

T3

38

auto[1]

2250982

1

T1

4

T2

7

T3

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10830104

1

T1

30

T2

45

T3

45

auto[1]

1747351

1

T33

5454

T34

9156

T49

65762

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	77164	1			T4	385		T6	1		T10	317
all_values[0]	auto[0]	auto[1]	18010	1			T33	94		T34	368		T192	3449
all_values[0]	auto[1]	auto[0]	639982	1			T1	2		T2	3		T3	3
all_values[0]	auto[1]	auto[1]	103341	1			T33	270		T34	286		T97	5
all_values[1]	auto[0]	auto[0]	707504	1			T1	2		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	130418	1			T33	354		T34	650		T49	5978
all_values[1]	auto[1]	auto[0]	285	1			T4	15		T39	9		T98	10
all_values[1]	auto[1]	auto[1]	290	1			T33	10		T34	5		T49	1
all_values[2]	auto[0]	auto[0]	707150	1			T1	2		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	131044	1			T33	356		T34	650		T49	5978
all_values[2]	auto[1]	auto[0]	94	1			T18	2		T138	4		T139	2
all_values[2]	auto[1]	auto[1]	209	1			T33	8		T34	5		T49	1
all_values[3]	auto[0]	auto[0]	713775	1			T1	2		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	124441	1			T33	351		T34	650		T97	4
all_values[3]	auto[1]	auto[1]	281	1			T33	12		T34	5		T97	5
all_values[4]	auto[0]	auto[0]	708957	1			T1	2		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	129299	1			T33	357		T34	653		T49	5976
all_values[4]	auto[1]	auto[0]	11	1			T42	1		T200	2		T201	3
all_values[4]	auto[1]	auto[1]	230	1			T33	7		T34	1		T49	1
all_values[5]	auto[0]	auto[0]	707232	1			T1	2		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	130993	1			T33	357		T34	653		T49	5975
all_values[5]	auto[1]	auto[1]	272	1			T33	7		T34	2		T49	3
all_values[6]	auto[0]	auto[0]	752545	1			T1	2		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	85691	1			T33	357		T34	650		T97	4
all_values[6]	auto[1]	auto[1]	261	1			T33	7		T34	3		T97	5
all_values[7]	auto[0]	auto[0]	726662	1			T1	2		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	84198	1			T33	323		T34	563		T49	5620
all_values[7]	auto[1]	auto[0]	23454	1			T4	238		T6	1		T10	89
all_values[7]	auto[1]	auto[1]	4183	1			T33	41		T34	88		T49	359
all_values[8]	auto[0]	auto[0]	707525	1			T1	2		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	130699	1			T33	354		T34	648		T49	5975
all_values[8]	auto[1]	auto[1]	273	1			T33	10		T34	7		T49	3
all_values[9]	auto[0]	auto[0]	167695	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	29354	1			T33	349		T34	642		T49	895
all_values[9]	auto[1]	auto[0]	582436	1			T2	1		T3	1		T4	5767
all_values[9]	auto[1]	auto[1]	59012	1			T33	14		T34	11		T49	5084
all_values[10]	auto[0]	auto[0]	747791	1			T1	2		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	90484	1			T33	350		T49	5977		T97	4
all_values[10]	auto[1]	auto[1]	222	1			T33	13		T49	1		T97	3
all_values[11]	auto[0]	auto[0]	2563	1			T4	9		T6	1		T10	9
all_values[11]	auto[0]	auto[1]	588	1			T33	34		T34	18		T49	6
all_values[11]	auto[1]	auto[0]	704951	1			T1	2		T2	3		T3	3
all_values[11]	auto[1]	auto[1]	130395	1			T33	330		T34	636		T49	5973
all_values[12]	auto[0]	auto[0]	710766	1			T1	2		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	127474	1			T33	352		T34	650		T49	5976
all_values[12]	auto[1]	auto[0]	17	1			T155	2		T202	2		T203	1
all_values[12]	auto[1]	auto[1]	240	1			T33	9		T34	2		T49	1
all_values[13]	auto[0]	auto[0]	718737	1			T1	2		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	119485	1			T33	357		T34	648		T97	4
all_values[13]	auto[1]	auto[1]	275	1			T33	7		T34	7		T97	5
all_values[14]	auto[0]	auto[0]	722808	1			T1	2		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	115421	1			T33	354		T34	652		T49	5978
all_values[14]	auto[1]	auto[1]	268	1			T33	10		T34	3		T49	1