Design Module List
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Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.07 94.73 88.08 97.22 69.05 87.18 98.15


Total modules in report: 40
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i2c_fifos 80.00 100.00 100.00 40.00
i2c_target_fsm 81.11 86.76 74.17 68.87 75.76 100.00
i2c_controller_fsm 84.13 90.80 77.37 66.67 85.79 100.00
i2c_bus_monitor 89.23 96.26 89.25 81.82 89.58
tlul_rsp_intg_gen 91.67 83.33 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 66.67 66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
prim_arbiter_tree 91.80 100.00 85.96 100.00 81.25
i2c_core 92.38 97.74 78.46 93.33 100.00
i2c_csr_assert_fpv 93.75 93.75
prim_subreg_arb 94.91 87.50 97.22 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=8,SwAccess=2,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=13,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=30,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=12,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=13,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=20,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=30,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=31,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=8,SwAccess=2,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=8,SwAccess=6,Mubi=0 ) 83.33 100.00 66.67
prim_subreg_arb ( parameter DW=9,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_generic_ram_1p 95.24 85.71 100.00 100.00
prim_fifo_sync 95.83 100.00 83.33 100.00 100.00
i2c_fifo_sync_sram_adapter 96.08 100.00 84.31 100.00 100.00
i2c_fifo_sync_sram_adapter 94.77 84.31 100.00 100.00
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 ) 100.00 100.00
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 ) 100.00 100.00
prim_subreg 96.32 100.00 96.10 92.86
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=8,SwAccess=2,RESVAL=0,Mubi=0 + DW=12,SwAccess=0,RESVAL=0,Mubi=0 + DW=13,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=9,SwAccess=0,RESVAL=0,Mubi=0 + DW=30,SwAccess=0,RESVAL=0,Mubi=0 + DW=7,SwAccess=0,RESVAL=0,Mubi=0 + DW=20,SwAccess=0,RESVAL=0,Mubi=0 + DW=31,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00 100.00
prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=12,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=13,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=20,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=30,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=31,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=8,SwAccess=2,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=8,SwAccess=6,RESVAL=0,Mubi=0 ) 80.95 100.00 57.14 85.71
prim_subreg ( parameter DW=9,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
i2c 98.48 100.00 100.00 93.91 100.00
tlul_adapter_reg 98.91 100.00 95.65 100.00 100.00
i2c_reg_top 99.71 100.00 98.85 100.00 100.00
prim_fifo_sync_cnt 100.00 100.00 100.00 100.00
prim_fifo_sync_cnt 100.00 100.00
prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 ) 100.00 100.00 100.00
prim_fifo_sync_cnt ( parameter Depth=266,Secure=0,PtrW=9,DepthW=9,WrapPtrW=10 ) 100.00 100.00 100.00
prim_fifo_sync_cnt ( parameter Depth=62,Secure=0,PtrW=6,DepthW=6,WrapPtrW=7 ) 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_onehot_check 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00 100.00
prim_intr_hw 100.00 100.00
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" ) 100.00 100.00 100.00 100.00
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" ) 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_ram_1p_adv 100.00 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb
prim_ram_1p
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