Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	838497	1			T1	2		T2	3		T3	3
all_pins[1]	838497	1			T1	2		T2	3		T3	3
all_pins[2]	838497	1			T1	2		T2	3		T3	3
all_pins[3]	838497	1			T1	2		T2	3		T3	3
all_pins[4]	838497	1			T1	2		T2	3		T3	3
all_pins[5]	838497	1			T1	2		T2	3		T3	3
all_pins[6]	838497	1			T1	2		T2	3		T3	3
all_pins[7]	838497	1			T1	2		T2	3		T3	3
all_pins[8]	838497	1			T1	2		T2	3		T3	3
all_pins[9]	838497	1			T1	2		T2	3		T3	3
all_pins[10]	838497	1			T1	2		T2	3		T3	3
all_pins[11]	838497	1			T1	2		T2	3		T3	3
all_pins[12]	838497	1			T1	2		T2	3		T3	3
all_pins[13]	838497	1			T1	2		T2	3		T3	3
all_pins[14]	838497	1			T1	2		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10332253	1			T1	26		T2	38		T3	38
values[0x1]	2245202	1			T1	4		T2	7		T3	7
transitions[0x0=>0x1]	2244277	1			T1	4		T2	7		T3	7
transitions[0x1=>0x0]	2243109	1			T1	3		T2	6		T3	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98533	1			T4	385		T6	1		T10	320
all_pins[0]	values[0x1]	739964	1			T1	2		T2	3		T3	3
all_pins[0]	transitions[0x0=>0x1]	739535	1			T1	2		T2	3		T3	3
all_pins[0]	transitions[0x1=>0x0]	97	1			T33	1		T34	1		T49	1
all_pins[1]	values[0x0]	837971	1			T1	2		T2	3		T3	3
all_pins[1]	values[0x1]	526	1			T4	17		T39	11		T33	5
all_pins[1]	transitions[0x0=>0x1]	498	1			T4	17		T39	11		T33	5
all_pins[1]	transitions[0x1=>0x0]	169	1			T18	2		T138	4		T139	2
all_pins[2]	values[0x0]	838300	1			T1	2		T2	3		T3	3
all_pins[2]	values[0x1]	197	1			T18	2		T138	4		T139	2
all_pins[2]	transitions[0x0=>0x1]	172	1			T18	2		T138	4		T139	2
all_pins[2]	transitions[0x1=>0x0]	99	1			T33	3		T34	4		T97	4
all_pins[3]	values[0x0]	838373	1			T1	2		T2	3		T3	3
all_pins[3]	values[0x1]	124	1			T33	4		T34	5		T97	4
all_pins[3]	transitions[0x0=>0x1]	87	1			T33	3		T34	5		T97	2
all_pins[3]	transitions[0x1=>0x0]	90	1			T33	2		T42	1		T200	3
all_pins[4]	values[0x0]	838370	1			T1	2		T2	3		T3	3
all_pins[4]	values[0x1]	127	1			T33	3		T42	1		T97	2
all_pins[4]	transitions[0x0=>0x1]	95	1			T33	2		T42	1		T97	2
all_pins[4]	transitions[0x1=>0x0]	105	1			T33	4		T49	1		T97	2
all_pins[5]	values[0x0]	838360	1			T1	2		T2	3		T3	3
all_pins[5]	values[0x1]	137	1			T33	5		T49	1		T97	2
all_pins[5]	transitions[0x0=>0x1]	101	1			T33	5		T49	1		T97	2
all_pins[5]	transitions[0x1=>0x0]	105	1			T33	2		T34	2		T97	3
all_pins[6]	values[0x0]	838356	1			T1	2		T2	3		T3	3
all_pins[6]	values[0x1]	141	1			T33	2		T34	2		T97	3
all_pins[6]	transitions[0x0=>0x1]	101	1			T33	2		T34	1		T192	3
all_pins[6]	transitions[0x1=>0x0]	30413	1			T4	263		T6	1		T10	111
all_pins[7]	values[0x0]	808044	1			T1	2		T2	3		T3	3
all_pins[7]	values[0x1]	30453	1			T4	263		T6	1		T10	111
all_pins[7]	transitions[0x0=>0x1]	30406	1			T4	263		T6	1		T10	111
all_pins[7]	transitions[0x1=>0x0]	98	1			T33	1		T34	2		T192	1
all_pins[8]	values[0x0]	838352	1			T1	2		T2	3		T3	3
all_pins[8]	values[0x1]	145	1			T33	4		T34	2		T192	4
all_pins[8]	transitions[0x0=>0x1]	106	1			T33	3		T34	2		T192	4
all_pins[8]	transitions[0x1=>0x0]	641337	1			T2	1		T3	1		T4	5767
all_pins[9]	values[0x0]	197121	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	641376	1			T2	1		T3	1		T4	5767
all_pins[9]	transitions[0x0=>0x1]	641347	1			T2	1		T3	1		T4	5767
all_pins[9]	transitions[0x1=>0x0]	73	1			T33	6		T192	3		T114	4
all_pins[10]	values[0x0]	838395	1			T1	2		T2	3		T3	3
all_pins[10]	values[0x1]	102	1			T33	8		T192	3		T114	4
all_pins[10]	transitions[0x0=>0x1]	72	1			T33	5		T192	2		T114	2
all_pins[10]	transitions[0x1=>0x0]	831482	1			T1	2		T2	3		T3	3
all_pins[11]	values[0x0]	6985	1			T4	9		T6	1		T10	9
all_pins[11]	values[0x1]	831512	1			T1	2		T2	3		T3	3
all_pins[11]	transitions[0x0=>0x1]	831459	1			T1	2		T2	3		T3	3
all_pins[11]	transitions[0x1=>0x0]	91	1			T33	3		T34	1		T97	1
all_pins[12]	values[0x0]	838353	1			T1	2		T2	3		T3	3
all_pins[12]	values[0x1]	144	1			T18	1		T33	6		T34	1
all_pins[12]	transitions[0x0=>0x1]	120	1			T18	1		T33	4		T34	1
all_pins[12]	transitions[0x1=>0x0]	104	1			T33	2		T34	5		T97	3
all_pins[13]	values[0x0]	838369	1			T1	2		T2	3		T3	3
all_pins[13]	values[0x1]	128	1			T33	4		T34	5		T97	3
all_pins[13]	transitions[0x0=>0x1]	100	1			T33	4		T34	5		T97	2
all_pins[13]	transitions[0x1=>0x0]	98	1			T33	7		T34	1		T192	4
all_pins[14]	values[0x0]	838371	1			T1	2		T2	3		T3	3
all_pins[14]	values[0x1]	126	1			T33	7		T34	1		T97	1
all_pins[14]	transitions[0x0=>0x1]	78	1			T33	4		T97	1		T192	2
all_pins[14]	transitions[0x1=>0x0]	738748	1			T1	1		T2	2		T3	2