Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	543	1			T33	21		T34	7		T49	4
all_values[1]	543	1			T33	21		T34	7		T49	4
all_values[2]	543	1			T33	21		T34	7		T49	4
all_values[3]	543	1			T33	21		T34	7		T49	4
all_values[4]	543	1			T33	21		T34	7		T49	4
all_values[5]	543	1			T33	21		T34	7		T49	4
all_values[6]	543	1			T33	21		T34	7		T49	4
all_values[7]	543	1			T33	21		T34	7		T49	4
all_values[8]	543	1			T33	21		T34	7		T49	4
all_values[9]	543	1			T33	21		T34	7		T49	4
all_values[10]	543	1			T33	21		T34	7		T49	4
all_values[11]	543	1			T33	21		T34	7		T49	4
all_values[12]	543	1			T33	21		T34	7		T49	4
all_values[13]	543	1			T33	21		T34	7		T49	4
all_values[14]	543	1			T33	21		T34	7		T49	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4161

1

T33

146

T34

52

T49

34

auto[1]

3984

1

T33

169

T34

53

T49

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T33

6

T34

21

T49

23

auto[1]

6965

1

T33

309

T34

84

T49

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4751

1

T33

174

T34

57

T49

43

auto[1]

3394

1

T33

141

T34

48

T49

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	54	1			T34	1		T49	3		T97	2
all_values[0]	auto[0]	auto[0]	auto[1]	114	1			T33	6		T192	4		T114	4
all_values[0]	auto[0]	auto[1]	auto[0]	33	1			T49	1		T97	2		T114	4
all_values[0]	auto[0]	auto[1]	auto[1]	110	1			T33	6		T34	1		T97	1
all_values[0]	auto[1]	auto[0]	auto[1]	116	1			T34	3		T97	1		T192	2
all_values[0]	auto[1]	auto[1]	auto[1]	116	1			T33	9		T34	2		T97	1
all_values[1]	auto[0]	auto[0]	auto[0]	40	1			T192	1		T115	1		T225	2
all_values[1]	auto[0]	auto[0]	auto[1]	109	1			T33	3		T49	2		T97	2
all_values[1]	auto[0]	auto[1]	auto[0]	22	1			T97	1		T114	1		T104	1
all_values[1]	auto[0]	auto[1]	auto[1]	125	1			T33	8		T34	2		T49	1
all_values[1]	auto[1]	auto[0]	auto[1]	126	1			T33	4		T34	2		T97	2
all_values[1]	auto[1]	auto[1]	auto[1]	121	1			T33	6		T34	3		T49	1
all_values[2]	auto[0]	auto[0]	auto[0]	49	1			T192	1		T100	1		T101	1
all_values[2]	auto[0]	auto[0]	auto[1]	126	1			T33	10		T34	1		T97	3
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T101	1		T104	1		T117	1
all_values[2]	auto[0]	auto[1]	auto[1]	128	1			T33	3		T34	1		T49	3
all_values[2]	auto[1]	auto[0]	auto[1]	101	1			T33	4		T34	3		T49	1
all_values[2]	auto[1]	auto[1]	auto[1]	108	1			T33	4		T34	2		T97	1
all_values[3]	auto[0]	auto[0]	auto[0]	37	1			T49	2		T50	1		T117	1
all_values[3]	auto[0]	auto[0]	auto[1]	130	1			T33	8		T34	1		T97	1
all_values[3]	auto[0]	auto[1]	auto[0]	37	1			T33	1		T49	2		T104	1
all_values[3]	auto[0]	auto[1]	auto[1]	115	1			T33	5		T34	1		T97	2
all_values[3]	auto[1]	auto[0]	auto[1]	113	1			T33	4		T97	1		T192	1
all_values[3]	auto[1]	auto[1]	auto[1]	111	1			T33	3		T34	5		T97	3
all_values[4]	auto[0]	auto[0]	auto[0]	44	1			T34	1		T97	1		T104	2
all_values[4]	auto[0]	auto[0]	auto[1]	123	1			T33	8		T34	2		T49	1
all_values[4]	auto[0]	auto[1]	auto[0]	35	1			T49	2		T97	2		T104	2
all_values[4]	auto[0]	auto[1]	auto[1]	111	1			T33	6		T34	3		T192	3
all_values[4]	auto[1]	auto[0]	auto[1]	118	1			T33	4		T34	1		T192	3
all_values[4]	auto[1]	auto[1]	auto[1]	112	1			T33	3		T49	1		T97	2
all_values[5]	auto[0]	auto[0]	auto[0]	46	1			T49	1		T100	2		T101	1
all_values[5]	auto[0]	auto[0]	auto[1]	116	1			T33	6		T34	1		T49	1
all_values[5]	auto[0]	auto[1]	auto[0]	24	1			T114	1		T100	2		T101	1
all_values[5]	auto[0]	auto[1]	auto[1]	135	1			T33	8		T34	3		T97	3
all_values[5]	auto[1]	auto[0]	auto[1]	106	1			T33	2		T34	3		T192	2
all_values[5]	auto[1]	auto[1]	auto[1]	116	1			T33	5		T49	2		T97	2
all_values[6]	auto[0]	auto[0]	auto[0]	53	1			T34	2		T49	2		T114	1
all_values[6]	auto[0]	auto[0]	auto[1]	108	1			T33	7		T192	3		T114	3
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T49	2		T114	1		T226	1
all_values[6]	auto[0]	auto[1]	auto[1]	123	1			T33	6		T34	2		T97	3
all_values[6]	auto[1]	auto[0]	auto[1]	107	1			T33	3		T34	2		T97	2
all_values[6]	auto[1]	auto[1]	auto[1]	123	1			T33	5		T34	1		T97	2
all_values[7]	auto[0]	auto[0]	auto[0]	52	1			T34	4		T50	1		T227	1
all_values[7]	auto[0]	auto[0]	auto[1]	102	1			T33	5		T97	1		T192	4
all_values[7]	auto[0]	auto[1]	auto[0]	31	1			T226	2		T228	2		T229	1
all_values[7]	auto[0]	auto[1]	auto[1]	149	1			T33	5		T34	2		T49	1
all_values[7]	auto[1]	auto[0]	auto[1]	113	1			T33	5		T49	2		T192	2
all_values[7]	auto[1]	auto[1]	auto[1]	96	1			T33	6		T34	1		T49	1
all_values[8]	auto[0]	auto[0]	auto[0]	42	1			T49	1		T114	3		T50	1
all_values[8]	auto[0]	auto[0]	auto[1]	123	1			T33	6		T34	2		T49	2
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T114	4		T230	2		T229	2
all_values[8]	auto[0]	auto[1]	auto[1]	118	1			T33	3		T97	1		T192	5
all_values[8]	auto[1]	auto[0]	auto[1]	110	1			T33	4		T34	1		T49	1
all_values[8]	auto[1]	auto[1]	auto[1]	125	1			T33	8		T34	4		T97	2
all_values[9]	auto[0]	auto[0]	auto[0]	57	1			T34	2		T50	3		T100	1
all_values[9]	auto[0]	auto[0]	auto[1]	109	1			T33	5		T34	1		T49	1
all_values[9]	auto[0]	auto[1]	auto[0]	44	1			T33	1		T97	2		T192	2
all_values[9]	auto[0]	auto[1]	auto[1]	120	1			T33	4		T192	5		T114	8
all_values[9]	auto[1]	auto[0]	auto[1]	112	1			T33	7		T34	2		T49	2
all_values[9]	auto[1]	auto[1]	auto[1]	101	1			T33	4		T34	2		T49	1
all_values[10]	auto[0]	auto[0]	auto[0]	47	1			T34	4		T97	1		T101	1
all_values[10]	auto[0]	auto[0]	auto[1]	111	1			T33	3		T49	1		T97	2
all_values[10]	auto[0]	auto[1]	auto[0]	48	1			T33	1		T34	3		T49	1
all_values[10]	auto[0]	auto[1]	auto[1]	115	1			T33	4		T49	1		T192	6
all_values[10]	auto[1]	auto[0]	auto[1]	119	1			T33	6		T49	1		T97	3
all_values[10]	auto[1]	auto[1]	auto[1]	103	1			T33	7		T192	4		T114	6
all_values[11]	auto[0]	auto[0]	auto[0]	29	1			T114	1		T50	2		T101	1
all_values[11]	auto[0]	auto[0]	auto[1]	128	1			T33	5		T49	1		T97	1
all_values[11]	auto[0]	auto[1]	auto[0]	29	1			T34	1		T114	1		T50	1
all_values[11]	auto[0]	auto[1]	auto[1]	119	1			T33	4		T34	4		T49	1
all_values[11]	auto[1]	auto[0]	auto[1]	119	1			T33	6		T49	1		T97	2
all_values[11]	auto[1]	auto[1]	auto[1]	119	1			T33	6		T34	2		T49	1
all_values[12]	auto[0]	auto[0]	auto[0]	52	1			T34	3		T49	2		T50	1
all_values[12]	auto[0]	auto[0]	auto[1]	103	1			T33	4		T34	2		T49	1
all_values[12]	auto[0]	auto[1]	auto[0]	24	1			T33	3		T192	1		T114	1
all_values[12]	auto[0]	auto[1]	auto[1]	124	1			T33	5		T97	1		T192	5
all_values[12]	auto[1]	auto[0]	auto[1]	125	1			T33	3		T34	2		T49	1
all_values[12]	auto[1]	auto[1]	auto[1]	115	1			T33	6		T97	2		T192	6
all_values[13]	auto[0]	auto[0]	auto[0]	56	1			T49	3		T100	2		T227	3
all_values[13]	auto[0]	auto[0]	auto[1]	125	1			T33	7		T97	3		T192	3
all_values[13]	auto[0]	auto[1]	auto[0]	35	1			T49	1		T192	1		T114	1
all_values[13]	auto[0]	auto[1]	auto[1]	110	1			T33	5		T34	3		T192	7
all_values[13]	auto[1]	auto[0]	auto[1]	110	1			T33	4		T34	2		T97	1
all_values[13]	auto[1]	auto[1]	auto[1]	107	1			T33	5		T34	2		T97	3
all_values[14]	auto[0]	auto[0]	auto[0]	47	1			T101	1		T228	2		T116	2
all_values[14]	auto[0]	auto[0]	auto[1]	120	1			T33	6		T34	1		T97	3
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T101	2		T226	1		T228	2
all_values[14]	auto[0]	auto[1]	auto[1]	122	1			T33	7		T34	3		T49	3
all_values[14]	auto[1]	auto[0]	auto[1]	114	1			T33	1		T34	3		T49	1
all_values[14]	auto[1]	auto[1]	auto[1]	112	1			T33	7		T97	2		T192	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal