Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44060666	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10759655

1

T1

15720

T2

335

T3

537

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53864148	1			T1	58604		T2	1369		T3	907
values[0x0]	477676	1			T1	345		T2	6		T3	454
values[0x1]	478497	1			T1	358		T2	10		T3	460

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31481712	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23338609

1

T1

28002

T2

569

T3

834

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	200114	1			T1	498		T2	4		T3	6
valid_sources[0x01]	203123	1			T1	13		T2	22		T3	10
valid_sources[0x02]	334387	1			T1	4		T2	11		T3	4
valid_sources[0x03]	203303	1			T1	3		T2	11		T3	9
valid_sources[0x04]	208716	1			T1	502		T2	7		T3	12
valid_sources[0x05]	211214	1			T1	9		T2	10		T3	3
valid_sources[0x06]	208331	1			T1	13		T2	7		T3	5
valid_sources[0x07]	210709	1			T1	499		T3	8		T4	1
valid_sources[0x08]	560217	1			T1	8		T2	2		T3	9
valid_sources[0x09]	213931	1			T1	10		T2	5		T3	4
valid_sources[0x0a]	212574	1			T1	9		T2	2		T3	8
valid_sources[0x0b]	203263	1			T1	2		T2	7		T3	14
valid_sources[0x0c]	200561	1			T1	501		T2	13		T3	5
valid_sources[0x0d]	213899	1			T1	500		T3	2		T4	1
valid_sources[0x0e]	194583	1			T1	4		T2	7		T3	11
valid_sources[0x0f]	204038	1			T1	507		T2	5		T3	6
valid_sources[0x10]	245403	1			T1	1		T2	3		T3	10
valid_sources[0x11]	199085	1			T1	4		T2	4		T3	8
valid_sources[0x12]	197942	1			T1	987		T2	13		T3	6
valid_sources[0x13]	208173	1			T1	506		T2	5		T3	7
valid_sources[0x14]	229721	1			T1	2		T3	10		T4	1
valid_sources[0x15]	220475	1			T1	1		T3	10		T4	3
valid_sources[0x16]	208426	1			T1	2		T2	1		T3	6
valid_sources[0x17]	207181	1			T1	2		T3	5		T4	6
valid_sources[0x18]	194764	1			T1	503		T2	10		T3	5
valid_sources[0x19]	200343	1			T1	3		T2	4		T3	6
valid_sources[0x1a]	205571	1			T1	501		T3	8		T4	23
valid_sources[0x1b]	207547	1			T1	506		T2	3		T3	9
valid_sources[0x1c]	201137	1			T1	4		T2	7		T3	10
valid_sources[0x1d]	208475	1			T1	513		T2	11		T3	5
valid_sources[0x1e]	229370	1			T1	7		T3	6		T4	7
valid_sources[0x1f]	206957	1			T1	17		T2	5		T3	8
valid_sources[0x20]	206536	1			T1	4		T2	8		T3	7
valid_sources[0x21]	230226	1			T1	1503		T2	1		T3	8
valid_sources[0x22]	208164	1			T1	4		T3	6		T4	2
valid_sources[0x23]	205961	1			T1	8		T2	10		T3	6
valid_sources[0x24]	221966	1			T1	2013		T2	1		T3	7
valid_sources[0x25]	191653	1			T1	501		T2	2		T3	4
valid_sources[0x26]	270509	1			T1	2		T2	8		T3	6
valid_sources[0x27]	204865	1			T1	10		T2	6		T3	7
valid_sources[0x28]	201979	1			T1	502		T2	2		T3	5
valid_sources[0x29]	202375	1			T1	1		T2	9		T3	8
valid_sources[0x2a]	255711	1			T1	3		T2	1		T3	7
valid_sources[0x2b]	201987	1			T1	498		T2	10		T3	5
valid_sources[0x2c]	212498	1			T1	4		T2	5		T3	5
valid_sources[0x2d]	210695	1			T1	9		T2	3		T3	5
valid_sources[0x2e]	208462	1			T1	8		T2	11		T3	10
valid_sources[0x2f]	203941	1			T1	505		T2	7		T3	12
valid_sources[0x30]	225311	1			T1	506		T3	8		T4	4
valid_sources[0x31]	217219	1			T1	6		T2	7		T3	12
valid_sources[0x32]	219711	1			T1	4		T2	4		T6	361
valid_sources[0x33]	204090	1			T1	503		T2	11		T3	7
valid_sources[0x34]	205373	1			T1	13		T2	4		T3	1
valid_sources[0x35]	229229	1			T1	506		T2	6		T3	8
valid_sources[0x36]	211883	1			T1	517		T2	8		T3	7
valid_sources[0x37]	205619	1			T2	1		T3	1		T4	6
valid_sources[0x38]	225088	1			T1	2453		T2	9		T3	5
valid_sources[0x39]	202980	1			T1	4		T2	15		T3	7
valid_sources[0x3a]	209718	1			T1	6		T2	1		T3	10
valid_sources[0x3b]	204608	1			T1	2		T2	1		T3	4
valid_sources[0x3c]	207497	1			T1	993		T2	4		T3	12
valid_sources[0x3d]	206223	1			T1	507		T2	5		T3	12
valid_sources[0x3e]	208332	1			T1	4		T3	8		T4	1
valid_sources[0x3f]	200930	1			T1	508		T3	5		T6	311
valid_sources[0x40]	202182	1			T1	4		T2	2		T3	10
valid_sources[0x41]	209496	1			T1	4		T2	9		T3	12
valid_sources[0x42]	209609	1			T1	8		T2	4		T3	8
valid_sources[0x43]	202929	1			T1	3		T2	19		T3	8
valid_sources[0x44]	202189	1			T1	3		T2	4		T3	9
valid_sources[0x45]	212405	1			T1	8		T2	2		T3	5
valid_sources[0x46]	199766	1			T1	11		T3	8		T6	318
valid_sources[0x47]	301339	1			T1	499		T2	8		T3	7
valid_sources[0x48]	218201	1			T1	2		T2	17		T3	5
valid_sources[0x49]	229636	1			T1	503		T2	6		T3	6
valid_sources[0x4a]	215939	1			T1	499		T2	3		T3	9
valid_sources[0x4b]	290991	1			T1	505		T2	4		T3	4
valid_sources[0x4c]	211048	1			T1	7		T2	9		T3	5
valid_sources[0x4d]	201114	1			T1	19		T2	6		T3	7
valid_sources[0x4e]	198498	1			T1	3		T2	6		T3	6
valid_sources[0x4f]	218219	1			T1	3		T2	8		T3	3
valid_sources[0x50]	214923	1			T2	4		T3	3		T4	11
valid_sources[0x51]	227610	1			T1	3		T2	2		T3	7
valid_sources[0x52]	222685	1			T2	17		T3	6		T4	9
valid_sources[0x53]	206437	1			T1	7		T3	7		T4	12
valid_sources[0x54]	205897	1			T1	998		T2	1		T3	8
valid_sources[0x55]	218848	1			T1	502		T2	7		T3	5
valid_sources[0x56]	202977	1			T1	9		T2	13		T3	7
valid_sources[0x57]	200402	1			T1	500		T2	6		T3	10
valid_sources[0x58]	211101	1			T1	3		T3	14		T4	1
valid_sources[0x59]	221997	1			T1	2		T2	2		T3	6
valid_sources[0x5a]	219540	1			T1	12		T2	4		T3	7
valid_sources[0x5b]	192729	1			T1	988		T2	7		T3	8
valid_sources[0x5c]	281039	1			T1	502		T2	1		T3	4
valid_sources[0x5d]	229212	1			T1	2		T2	6		T3	8
valid_sources[0x5e]	196877	1			T1	10		T2	4		T3	12
valid_sources[0x5f]	206052	1			T1	499		T2	2		T3	13
valid_sources[0x60]	199323	1			T1	6		T2	4		T3	10
valid_sources[0x61]	205812	1			T1	1486		T2	4		T3	5
valid_sources[0x62]	214293	1			T1	5		T2	1		T3	8
valid_sources[0x63]	194453	1			T1	509		T2	1		T3	3
valid_sources[0x64]	198194	1			T1	16		T2	2		T3	7
valid_sources[0x65]	199167	1			T1	6		T2	8		T3	3
valid_sources[0x66]	209688	1			T1	5		T3	5		T5	85
valid_sources[0x67]	204357	1			T1	8		T2	4		T3	9
valid_sources[0x68]	203746	1			T1	986		T2	19		T3	9
valid_sources[0x69]	201688	1			T1	498		T2	1		T3	5
valid_sources[0x6a]	204517	1			T1	1		T2	7		T3	7
valid_sources[0x6b]	204325	1			T1	6		T2	11		T3	7
valid_sources[0x6c]	201011	1			T1	9		T2	1		T3	9
valid_sources[0x6d]	201326	1			T1	9		T2	6		T3	3
valid_sources[0x6e]	216853	1			T1	8		T2	1		T3	7
valid_sources[0x6f]	220148	1			T1	503		T2	18		T3	6
valid_sources[0x70]	217652	1			T1	8		T2	3		T3	8
valid_sources[0x71]	217533	1			T1	4		T2	4		T3	9
valid_sources[0x72]	219628	1			T1	500		T2	16		T3	11
valid_sources[0x73]	225914	1			T1	5		T2	7		T3	7
valid_sources[0x74]	197530	1			T1	491		T2	3		T3	9
valid_sources[0x75]	202870	1			T1	2		T2	1		T3	6
valid_sources[0x76]	211587	1			T1	4		T2	2		T3	12
valid_sources[0x77]	210694	1			T1	517		T2	9		T3	12
valid_sources[0x78]	210286	1			T1	4		T2	9		T3	9
valid_sources[0x79]	211750	1			T1	6		T2	8		T3	13
valid_sources[0x7a]	208336	1			T1	18		T2	6		T3	3
valid_sources[0x7b]	191573	1			T1	498		T2	18		T3	12
valid_sources[0x7c]	208659	1			T1	10		T3	5		T4	7
valid_sources[0x7d]	203824	1			T1	500		T2	3		T3	6
valid_sources[0x7e]	205955	1			T1	5		T2	6		T3	7
valid_sources[0x7f]	197221	1			T1	998		T2	9		T3	5
valid_sources[0x80]	206227	1			T1	11		T3	7		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10342292

1

T1

15291

T2

323

T3

271

values[0x0]

all_enables

biggest_size

246090

1

T1

231

T2

5

T3

167

values[0x1]

all_enables

biggest_size

171273

1

T1

198

T2

7

T3

99