Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_subreg_ext
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_val_scl_rx 66.67 66.67
tb.dut.u_reg.u_val_sda_rx 66.67 66.67
tb.dut.u_reg.u_acq_fifo_next_data 66.67 66.67
tb.dut.u_reg.u_intr_test_fmt_threshold 100.00 100.00
tb.dut.u_reg.u_intr_test_rx_threshold 100.00 100.00
tb.dut.u_reg.u_intr_test_acq_threshold 100.00 100.00
tb.dut.u_reg.u_intr_test_rx_overflow 100.00 100.00
tb.dut.u_reg.u_intr_test_controller_halt 100.00 100.00
tb.dut.u_reg.u_intr_test_scl_interference 100.00 100.00
tb.dut.u_reg.u_intr_test_sda_interference 100.00 100.00
tb.dut.u_reg.u_intr_test_stretch_timeout 100.00 100.00
tb.dut.u_reg.u_intr_test_sda_unstable 100.00 100.00
tb.dut.u_reg.u_intr_test_cmd_complete 100.00 100.00
tb.dut.u_reg.u_intr_test_tx_stretch 100.00 100.00
tb.dut.u_reg.u_intr_test_tx_threshold 100.00 100.00
tb.dut.u_reg.u_intr_test_acq_stretch 100.00 100.00
tb.dut.u_reg.u_intr_test_unexp_stop 100.00 100.00
tb.dut.u_reg.u_intr_test_host_timeout 100.00 100.00
tb.dut.u_reg.u_alert_test 100.00 100.00
tb.dut.u_reg.u_status_fmtfull 100.00 100.00
tb.dut.u_reg.u_status_rxfull 100.00 100.00
tb.dut.u_reg.u_status_fmtempty 100.00 100.00
tb.dut.u_reg.u_status_hostidle 100.00 100.00
tb.dut.u_reg.u_status_targetidle 100.00 100.00
tb.dut.u_reg.u_status_rxempty 100.00 100.00
tb.dut.u_reg.u_status_txfull 100.00 100.00
tb.dut.u_reg.u_status_acqfull 100.00 100.00
tb.dut.u_reg.u_status_txempty 100.00 100.00
tb.dut.u_reg.u_status_acqempty 100.00 100.00
tb.dut.u_reg.u_status_ack_ctrl_stretch 100.00 100.00
tb.dut.u_reg.u_rdata 100.00 100.00
tb.dut.u_reg.u_host_fifo_status_fmtlvl 100.00 100.00
tb.dut.u_reg.u_host_fifo_status_rxlvl 100.00 100.00
tb.dut.u_reg.u_target_fifo_status_txlvl 100.00 100.00
tb.dut.u_reg.u_target_fifo_status_acqlvl 100.00 100.00
tb.dut.u_reg.u_acqdata_abyte 100.00 100.00
tb.dut.u_reg.u_acqdata_signal 100.00 100.00
tb.dut.u_reg.u_target_ack_ctrl_nbytes 100.00 100.00
tb.dut.u_reg.u_target_ack_ctrl_nack 100.00 100.00



Module Instance : tb.dut.u_reg.u_val_scl_rx

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_val_sda_rx

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_acq_fifo_next_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_fmt_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_rx_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_acq_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_rx_overflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_controller_halt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_scl_interference

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_sda_interference

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_stretch_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_sda_unstable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_cmd_complete

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_tx_stretch

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_tx_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_acq_stretch

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_unexp_stop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_host_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_alert_test

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_fmtfull

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_rxfull

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_fmtempty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_hostidle

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_targetidle

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_rxempty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_txfull

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_acqfull

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_txempty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_acqempty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_status_ack_ctrl_stretch

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_rdata

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_host_fifo_status_fmtlvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_host_fifo_status_rxlvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_target_fifo_status_txlvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_target_fifo_status_acqlvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_acqdata_abyte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_acqdata_signal

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_target_ack_ctrl_nbytes

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_target_ack_ctrl_nack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.50 100.00 97.98 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_subreg_ext
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_val_scl_rx
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN30100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 0 1

Line Coverage for Instance : tb.dut.u_reg.u_val_sda_rx
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN30100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 0 1

Line Coverage for Instance : tb.dut.u_reg.u_acq_fifo_next_data
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN30100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 0 1

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_fmt_threshold
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_rx_threshold
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_acq_threshold
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_rx_overflow
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_controller_halt
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_scl_interference
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_sda_interference
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_stretch_timeout
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_sda_unstable
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_cmd_complete
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_tx_stretch
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_tx_threshold
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_acq_stretch
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_unexp_stop
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_host_timeout
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_alert_test
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_status_fmtfull
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_rxfull
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_fmtempty
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_hostidle
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_targetidle
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_rxempty
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_txfull
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_acqfull
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_txempty
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_acqempty
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_status_ack_ctrl_stretch
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_rdata
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_host_fifo_status_fmtlvl
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_host_fifo_status_rxlvl
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_target_fifo_status_txlvl
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_target_fifo_status_acqlvl
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_acqdata_abyte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_acqdata_signal
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_target_ack_ctrl_nbytes
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_target_ack_ctrl_nack
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%