Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	410789993	0	0	0
ctrl_rd_A	410789993	2484	0	0
host_fifo_config_rd_A	410789993	5777	0	0
host_nack_handler_timeout_rd_A	410789993	1471	0	0
host_timeout_ctrl_rd_A	410789993	1455	0	0
intr_enable_rd_A	410789993	3831	0	0
ovrd_rd_A	410789993	2358	0	0
target_fifo_config_rd_A	410789993	1707	0	0
target_id_rd_A	410789993	1848	0	0
target_timeout_ctrl_rd_A	410789993	1619	0	0
timeout_ctrl_rd_A	410789993	1801	0	0
timing0_rd_A	410789993	1750	0	0
timing1_rd_A	410789993	1645	0	0
timing2_rd_A	410789993	1482	0	0
timing3_rd_A	410789993	1689	0	0
timing4_rd_A	410789993	1459	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	2484	0	0
T95	11168	52	0	0
T96	2269	18	0	0
T97	1229	19	0	0
T98	11807	109	0	0
T99	3787	35	0	0
T100	14288	203	0	0
T101	4092	15	0	0
T102	2336	4	0	0
T103	3388	19	0	0
T104	7025	58	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	5777	0	0
T26	88841	0	0	0
T78	100785	0	0	0
T81	440243	0	0	0
T105	489324	102	0	0
T106	0	178	0	0
T107	0	107	0	0
T108	0	88	0	0
T109	0	127	0	0
T110	0	69	0	0
T111	0	116	0	0
T112	0	160	0	0
T113	0	231	0	0
T114	0	326	0	0
T115	134257	0	0	0
T116	74083	0	0	0
T117	129219	0	0	0
T118	126165	0	0	0
T119	82782	0	0	0
T120	41661	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1471	0	0
T95	11168	40	0	0
T96	2269	7	0	0
T97	1229	15	0	0
T98	11807	94	0	0
T99	3787	8	0	0
T100	14288	50	0	0
T101	4092	12	0	0
T102	2336	18	0	0
T103	3388	20	0	0
T104	7025	21	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1455	0	0
T95	11168	37	0	0
T96	2269	6	0	0
T97	1229	4	0	0
T98	11807	153	0	0
T99	3787	10	0	0
T100	14288	41	0	0
T101	4092	14	0	0
T102	2336	12	0	0
T103	3388	17	0	0
T104	7025	51	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	3831	0	0
T60	467468	0	0	0
T61	0	26	0	0
T84	469689	2	0	0
T85	886963	0	0	0
T95	0	15	0	0
T96	0	3	0	0
T97	0	1	0	0
T121	0	9	0	0
T122	0	9	0	0
T123	0	25	0	0
T124	0	27	0	0
T125	0	10	0	0
T126	12984	0	0	0
T127	253728	0	0	0
T128	110133	0	0	0
T129	1057	0	0	0
T130	44011	0	0	0
T131	6821	0	0	0
T132	186888	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	2358	0	0
T12	97833	0	0	0
T19	42405	0	0	0
T35	169771	0	0	0
T57	16055	0	0	0
T74	1277	59	0	0
T94	1776	44	0	0
T133	0	44	0	0
T134	0	44	0	0
T135	0	52	0	0
T136	0	24	0	0
T137	0	66	0	0
T138	0	27	0	0
T139	0	60	0	0
T140	0	36	0	0
T141	139307	0	0	0
T142	52746	0	0	0
T143	203732	0	0	0
T144	138765	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1707	0	0
T95	11168	41	0	0
T96	2269	2	0	0
T97	1229	3	0	0
T98	11807	116	0	0
T99	3787	19	0	0
T100	14288	75	0	0
T101	4092	21	0	0
T102	2336	13	0	0
T103	3388	10	0	0
T104	7025	46	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1848	0	0
T95	11168	16	0	0
T96	2269	12	0	0
T97	1229	8	0	0
T98	11807	115	0	0
T99	3787	45	0	0
T100	14288	89	0	0
T101	4092	1	0	0
T102	2336	2	0	0
T103	3388	28	0	0
T104	7025	49	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1619	0	0
T95	11168	22	0	0
T96	2269	9	0	0
T97	1229	6	0	0
T98	11807	121	0	0
T99	3787	21	0	0
T100	14288	69	0	0
T101	4092	38	0	0
T102	2336	13	0	0
T103	3388	25	0	0
T104	7025	23	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1801	0	0
T95	11168	43	0	0
T96	2269	5	0	0
T97	1229	1	0	0
T98	11807	110	0	0
T99	3787	26	0	0
T100	14288	72	0	0
T101	4092	13	0	0
T102	2336	23	0	0
T103	3388	25	0	0
T104	7025	40	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1750	0	0
T95	11168	50	0	0
T97	1229	14	0	0
T98	11807	125	0	0
T99	3787	25	0	0
T100	14288	103	0	0
T101	4092	61	0	0
T102	2336	27	0	0
T103	3388	27	0	0
T104	7025	29	0	0
T145	3311	1	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1645	0	0
T95	11168	20	0	0
T96	2269	2	0	0
T97	1229	4	0	0
T98	11807	151	0	0
T99	3787	24	0	0
T100	14288	56	0	0
T101	4092	26	0	0
T102	2336	3	0	0
T103	3388	18	0	0
T104	7025	44	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1482	0	0
T95	11168	43	0	0
T97	1229	10	0	0
T98	11807	125	0	0
T99	3787	14	0	0
T100	14288	62	0	0
T101	4092	18	0	0
T102	2336	14	0	0
T103	3388	19	0	0
T104	7025	47	0	0
T145	3311	5	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1689	0	0
T95	11168	66	0	0
T96	2269	4	0	0
T97	1229	8	0	0
T98	11807	109	0	0
T99	3787	20	0	0
T100	14288	40	0	0
T101	4092	25	0	0
T102	2336	8	0	0
T103	3388	25	0	0
T104	7025	82	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410789993	1459	0	0
T95	11168	33	0	0
T96	2269	4	0	0
T97	1229	3	0	0
T98	11807	108	0	0
T99	3787	22	0	0
T100	14288	65	0	0
T101	4092	9	0	0
T102	2336	12	0	0
T103	3388	27	0	0
T104	7025	69	0	0