Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1008147	1			T2	7313		T3	4		T4	3
all_values[1]	1008147	1			T2	7313		T3	4		T4	3
all_values[2]	1008147	1			T2	7313		T3	4		T4	3
all_values[3]	1008147	1			T2	7313		T3	4		T4	3
all_values[4]	1008147	1			T2	7313		T3	4		T4	3
all_values[5]	1008147	1			T2	7313		T3	4		T4	3
all_values[6]	1008147	1			T2	7313		T3	4		T4	3
all_values[7]	1008147	1			T2	7313		T3	4		T4	3
all_values[8]	1008147	1			T2	7313		T3	4		T4	3
all_values[9]	1008147	1			T2	7313		T3	4		T4	3
all_values[10]	1008147	1			T2	7313		T3	4		T4	3
all_values[11]	1008147	1			T2	7313		T3	4		T4	3
all_values[12]	1008147	1			T2	7313		T3	4		T4	3
all_values[13]	1008147	1			T2	7313		T3	4		T4	3
all_values[14]	1008147	1			T2	7313		T3	4		T4	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12425950

1

T2

88601

T3

51

T4

39

auto[1]

2696255

1

T2

21094

T3

9

T4

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13008496

1

T2

109695

T3

60

T4

45

auto[1]

2113709

1

T31

17957

T42

108635

T54

13221

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	109063	1			T2	576		T4	1		T5	3
all_values[0]	auto[0]	auto[1]	23355	1			T31	56		T42	80		T54	16
all_values[0]	auto[1]	auto[0]	756136	1			T2	6737		T3	4		T4	2
all_values[0]	auto[1]	auto[1]	119593	1			T31	1325		T42	7162		T54	988
all_values[1]	auto[0]	auto[0]	859436	1			T2	7313		T3	4		T4	3
all_values[1]	auto[0]	auto[1]	148213	1			T42	7185		T54	1000		T186	1265
all_values[1]	auto[1]	auto[0]	222	1			T31	1		T33	3		T34	2
all_values[1]	auto[1]	auto[1]	276	1			T42	58		T54	5		T186	1
all_values[2]	auto[0]	auto[0]	858211	1			T2	7313		T3	4		T4	3
all_values[2]	auto[0]	auto[1]	149651	1			T31	1379		T42	7240		T54	998
all_values[2]	auto[1]	auto[0]	107	1			T18	3		T210	2		T211	2
all_values[2]	auto[1]	auto[1]	178	1			T31	2		T42	3		T54	6
all_values[3]	auto[0]	auto[0]	882324	1			T2	7313		T3	4		T4	3
all_values[3]	auto[0]	auto[1]	125626	1			T31	1378		T42	7238		T54	999
all_values[3]	auto[1]	auto[1]	197	1			T31	4		T42	4		T54	6
all_values[4]	auto[0]	auto[0]	887574	1			T2	7313		T3	4		T4	3
all_values[4]	auto[0]	auto[1]	120386	1			T31	1379		T42	7239		T54	1000
all_values[4]	auto[1]	auto[0]	12	1			T57	2		T212	1		T213	1
all_values[4]	auto[1]	auto[1]	175	1			T31	1		T42	4		T54	4
all_values[5]	auto[0]	auto[0]	858271	1			T2	7313		T3	4		T4	3
all_values[5]	auto[0]	auto[1]	149619	1			T31	1378		T42	7236		T54	999
all_values[5]	auto[1]	auto[1]	257	1			T31	4		T42	3		T54	5
all_values[6]	auto[0]	auto[0]	876161	1			T2	7313		T3	4		T4	3
all_values[6]	auto[0]	auto[1]	131774	1			T31	1379		T42	7239		T54	79
all_values[6]	auto[1]	auto[1]	212	1			T31	2		T42	4		T54	4
all_values[7]	auto[0]	auto[0]	831544	1			T2	7041		T3	4		T4	2
all_values[7]	auto[0]	auto[1]	144212	1			T31	1224		T42	7000		T54	77
all_values[7]	auto[1]	auto[0]	28001	1			T2	272		T4	1		T5	5
all_values[7]	auto[1]	auto[1]	4390	1			T31	158		T42	240		T54	3
all_values[8]	auto[0]	auto[0]	858277	1			T2	7313		T3	4		T4	3
all_values[8]	auto[0]	auto[1]	149671	1			T31	1381		T42	7239		T54	1000
all_values[8]	auto[1]	auto[1]	199	1			T42	4		T54	4		T186	1
all_values[9]	auto[0]	auto[0]	202296	1			T2	532		T3	3		T4	2
all_values[9]	auto[0]	auto[1]	25212	1			T31	1341		T42	397		T54	983
all_values[9]	auto[1]	auto[0]	673121	1			T2	6781		T3	1		T4	1
all_values[9]	auto[1]	auto[1]	107518	1			T31	40		T42	6846		T54	21
all_values[10]	auto[0]	auto[0]	862067	1			T2	7313		T3	4		T4	3
all_values[10]	auto[0]	auto[1]	145898	1			T31	1381		T42	7240		T54	1001
all_values[10]	auto[1]	auto[1]	182	1			T31	1		T42	3		T54	3
all_values[11]	auto[0]	auto[0]	2741	1			T2	9		T4	1		T5	3
all_values[11]	auto[0]	auto[1]	545	1			T31	17		T42	12		T54	5
all_values[11]	auto[1]	auto[0]	866189	1			T2	7304		T3	4		T4	2
all_values[11]	auto[1]	auto[1]	138672	1			T31	1364		T42	7231		T54	1000
all_values[12]	auto[0]	auto[0]	859834	1			T2	7313		T3	4		T4	3
all_values[12]	auto[0]	auto[1]	148111	1			T42	7239		T54	1001		T186	1266
all_values[12]	auto[1]	auto[0]	21	1			T211	1		T214	1		T215	1
all_values[12]	auto[1]	auto[1]	181	1			T42	4		T54	4		T186	3
all_values[13]	auto[0]	auto[0]	876929	1			T2	7313		T3	4		T4	3
all_values[13]	auto[0]	auto[1]	131004	1			T31	1381		T42	7236		T54	1000
all_values[13]	auto[1]	auto[1]	214	1			T31	1		T42	7		T54	5
all_values[14]	auto[0]	auto[0]	859959	1			T2	7313		T3	4		T4	3
all_values[14]	auto[0]	auto[1]	147986	1			T31	1380		T42	7239		T54	996
all_values[14]	auto[1]	auto[1]	202	1			T31	1		T42	3		T54	9