| | | | | | | | |
tb |
90.66 |
96.51 |
89.88 |
97.22 |
68.45 |
93.48 |
98.44 |
| dut |
90.66 |
96.51 |
89.88 |
97.22 |
68.45 |
93.48 |
98.44 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| i2c_core |
86.58 |
94.99 |
84.60 |
|
68.45 |
90.15 |
94.69 |
| intr_hw_acq_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_acq_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_cmd_complete |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_controller_halt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_fmt_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_host_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_rx_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_rx_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_scl_interference |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_sda_interference |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_sda_unstable |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_stretch_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_tx_stretch |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_tx_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_unexp_stop |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_fifos |
94.57 |
99.86 |
86.27 |
|
|
98.65 |
93.48 |
| u_acq_fifo_sram_adapter |
96.32 |
100.00 |
86.79 |
|
|
98.51 |
100.00 |
| u_inp_buf |
94.32 |
100.00 |
81.82 |
|
|
95.45 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
94.10 |
100.00 |
90.00 |
|
|
92.31 |
|
| u_oup_buf |
97.73 |
100.00 |
90.91 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_sram_ptrs |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_fmt_fifo_sram_adapter |
96.32 |
100.00 |
86.79 |
|
|
98.51 |
100.00 |
| u_inp_buf |
94.32 |
100.00 |
81.82 |
|
|
95.45 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
94.10 |
100.00 |
90.00 |
|
|
92.31 |
|
| u_oup_buf |
97.73 |
100.00 |
90.91 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_sram_ptrs |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_ram_1p |
99.02 |
97.06 |
|
|
|
100.00 |
100.00 |
| u_mem |
95.24 |
85.71 |
|
|
|
100.00 |
100.00 |
| gen_generic.u_impl_generic |
95.24 |
85.71 |
|
|
|
100.00 |
100.00 |
| u_req_d_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_write_d_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_ram_arbiter |
92.02 |
100.00 |
86.84 |
|
|
100.00 |
81.25 |
| u_rx_fifo_sram_adapter |
96.32 |
100.00 |
86.79 |
|
|
98.51 |
100.00 |
| u_inp_buf |
94.32 |
100.00 |
81.82 |
|
|
95.45 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
94.10 |
100.00 |
90.00 |
|
|
92.31 |
|
| u_oup_buf |
97.16 |
100.00 |
88.64 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_sram_ptrs |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_tx_fifo_sram_adapter |
95.70 |
100.00 |
84.28 |
|
|
98.51 |
100.00 |
| u_inp_buf |
94.32 |
100.00 |
81.82 |
|
|
95.45 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
94.10 |
100.00 |
90.00 |
|
|
92.31 |
|
| u_oup_buf |
97.16 |
100.00 |
88.64 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_sram_ptrs |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_i2c_bus_monitor |
89.50 |
96.26 |
90.32 |
|
81.82 |
89.58 |
|
| u_i2c_controller_fsm |
83.98 |
90.80 |
76.64 |
|
66.67 |
85.79 |
100.00 |
| u_i2c_sync_scl |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_i2c_sync_sda |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_i2c_target_fsm |
80.92 |
86.76 |
74.17 |
|
67.92 |
75.76 |
100.00 |
| i2c_csr_assert |
93.75 |
|
|
|
|
|
93.75 |
| tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
| u_reg |
98.63 |
98.59 |
96.99 |
100.00 |
|
97.58 |
100.00 |
| subtree... |
|
|
|
|
|
|
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