Group : i2c_env_pkg::i2c_fifo_reset_cg
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Group : i2c_env_pkg::i2c_fifo_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
81.82 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv


Summary for Group i2c_env_pkg::i2c_fifo_reset_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 20 2 18 90.00
Crosses 24 6 18 75.00


Variables for Group i2c_env_pkg::i2c_fifo_reset_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_acq_overflow 2 1 1 50.00 100 1 1 2
cp_acq_threshold 2 0 2 100.00 100 1 1 2
cp_acqrst 2 0 2 100.00 100 1 1 2
cp_fmt_threshold 2 0 2 100.00 100 1 1 2
cp_fmtrst 2 0 2 100.00 100 1 1 2
cp_rx_overflow 2 1 1 50.00 100 1 1 2
cp_rx_threshold 2 0 2 100.00 100 1 1 2
cp_rxrst 2 0 2 100.00 100 1 1 2
cp_tx_threshold 2 0 2 100.00 100 1 1 2
cp_txrst 2 0 2 100.00 100 1 1 2


Crosses for Group i2c_env_pkg::i2c_fifo_reset_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cp_fmt_threshold_cross 4 0 4 100.00 100 1 1 0
cp_rx_threshold_cross 4 1 3 75.00 100 1 1 0
cp_acq_threshold_cross 4 1 3 75.00 100 1 1 0
cp_rx_overflow_cross 4 2 2 50.00 100 1 1 0
cp_acq_overflow_cross 4 2 2 50.00 100 1 1 0
cp_tx_threshold_cross 4 0 4 100.00 100 1 1 0


Summary for Variable cp_acq_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_acq_overflow

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13295 1 T2 1 T3 1 T4 1


Summary for Variable cp_acq_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_threshold

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 13272 1 T2 1 T3 1 T4 1
auto[1] 23 1 T194 23 - - - -


Summary for Variable cp_acqrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acqrst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3513 1 T17 54 T27 45 T51 20
auto[1] 9782 1 T2 1 T3 1 T4 1


Summary for Variable cp_fmt_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmt_threshold

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3090 1 T2 1 T3 1 T4 1
auto[1] 10205 1 T31 5 T17 108 T27 90


Summary for Variable cp_fmtrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmtrst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 10499 1 T17 108 T27 90 T51 10
auto[1] 2796 1 T2 1 T3 1 T4 1


Summary for Variable cp_rx_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_rx_overflow

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13295 1 T2 1 T3 1 T4 1


Summary for Variable cp_rx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_threshold

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 13271 1 T2 1 T3 1 T4 1
auto[1] 24 1 T189 1 T190 1 T191 1


Summary for Variable cp_rxrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rxrst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 10856 1 T17 108 T27 90 T51 20
auto[1] 2439 1 T2 1 T3 1 T4 1


Summary for Variable cp_tx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_threshold

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 5615 1 T2 1 T3 1 T4 1
auto[1] 7680 1 T31 5 T17 101 T27 88


Summary for Variable cp_txrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txrst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3142 1 T51 20 T52 14 T53 18
auto[1] 10153 1 T2 1 T3 1 T4 1


Summary for Cross cp_fmt_threshold_cross

Samples crossed: cp_fmt_threshold cp_fmtrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_fmt_threshold_cross

Bins
cp_fmt_threshold   cp_fmtrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 381 1 T51 10 T52 7 T53 9
auto[0] auto[1] 2709 1 T2 1 T3 1 T4 1
auto[1] auto[0] 10118 1 T17 108 T27 90 T13 80
auto[1] auto[1] 87 1 T31 5 T42 2 T48 1


Summary for Cross cp_rx_threshold_cross

Samples crossed: cp_rx_threshold cp_rxrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cp_rx_threshold_cross

Uncovered bins
cp_rx_thresholdcp_rxrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_rx_threshold   cp_rxrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 10856 1 T17 108 T27 90 T51 20
auto[0] auto[1] 2415 1 T2 1 T3 1 T4 1
auto[1] auto[1] 24 1 T189 1 T190 1 T191 1


Summary for Cross cp_acq_threshold_cross

Samples crossed: cp_acq_threshold cp_fmtrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cp_acq_threshold_cross

Uncovered bins
cp_acq_thresholdcp_fmtrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_acq_threshold   cp_fmtrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 10476 1 T17 108 T27 90 T51 10
auto[0] auto[1] 2796 1 T2 1 T3 1 T4 1
auto[1] auto[0] 23 1 T194 23 - - - -


Summary for Cross cp_rx_overflow_cross

Samples crossed: cp_rx_overflow cp_rxrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cp_rx_overflow_cross

Element holes
cp_rx_overflowcp_rxrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Covered bins
cp_rx_overflow   cp_rxrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 10856 1 T17 108 T27 90 T51 20
auto[0] auto[1] 2439 1 T2 1 T3 1 T4 1


Summary for Cross cp_acq_overflow_cross

Samples crossed: cp_acq_overflow cp_acqrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cp_acq_overflow_cross

Element holes
cp_acq_overflowcp_acqrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Covered bins
cp_acq_overflow   cp_acqrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 3513 1 T17 54 T27 45 T51 20
auto[0] auto[1] 9782 1 T2 1 T3 1 T4 1


Summary for Cross cp_tx_threshold_cross

Samples crossed: cp_tx_threshold cp_txrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_tx_threshold_cross

Bins
cp_tx_threshold   cp_txrst   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 1534 1 T51 20 T52 14 T53 18
auto[0] auto[1] 4081 1 T2 1 T3 1 T4 1
auto[1] auto[0] 1608 1 T30 6 T189 2 T195 5
auto[1] auto[1] 6072 1 T31 5 T17 101 T27 88