Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1008147	1			T2	7313		T3	4		T4	3
all_pins[1]	1008147	1			T2	7313		T3	4		T4	3
all_pins[2]	1008147	1			T2	7313		T3	4		T4	3
all_pins[3]	1008147	1			T2	7313		T3	4		T4	3
all_pins[4]	1008147	1			T2	7313		T3	4		T4	3
all_pins[5]	1008147	1			T2	7313		T3	4		T4	3
all_pins[6]	1008147	1			T2	7313		T3	4		T4	3
all_pins[7]	1008147	1			T2	7313		T3	4		T4	3
all_pins[8]	1008147	1			T2	7313		T3	4		T4	3
all_pins[9]	1008147	1			T2	7313		T3	4		T4	3
all_pins[10]	1008147	1			T2	7313		T3	4		T4	3
all_pins[11]	1008147	1			T2	7313		T3	4		T4	3
all_pins[12]	1008147	1			T2	7313		T3	4		T4	3
all_pins[13]	1008147	1			T2	7313		T3	4		T4	3
all_pins[14]	1008147	1			T2	7313		T3	4		T4	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	12430938	1			T2	88549		T3	51		T4	39
values[0x1]	2691267	1			T2	21146		T3	9		T4	6
transitions[0x0=>0x1]	2690532	1			T2	21146		T3	9		T4	6
transitions[0x1=>0x0]	2689325	1			T2	21145		T3	8		T4	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	135711	1			T2	574		T4	1		T5	19
all_pins[0]	values[0x1]	872436	1			T2	6739		T3	4		T4	2
all_pins[0]	transitions[0x0=>0x1]	872074	1			T2	6739		T3	4		T4	2
all_pins[0]	transitions[0x1=>0x0]	75	1			T42	1		T54	2		T59	1
all_pins[1]	values[0x0]	1007710	1			T2	7313		T3	4		T4	3
all_pins[1]	values[0x1]	437	1			T31	1		T33	5		T34	2
all_pins[1]	transitions[0x0=>0x1]	419	1			T31	1		T33	5		T34	2
all_pins[1]	transitions[0x1=>0x0]	170	1			T31	1		T18	3		T42	1
all_pins[2]	values[0x0]	1007959	1			T2	7313		T3	4		T4	3
all_pins[2]	values[0x1]	188	1			T31	1		T18	3		T42	2
all_pins[2]	transitions[0x0=>0x1]	173	1			T31	1		T18	3		T42	1
all_pins[2]	transitions[0x1=>0x0]	78	1			T31	1		T42	2		T54	2
all_pins[3]	values[0x0]	1008054	1			T2	7313		T3	4		T4	3
all_pins[3]	values[0x1]	93	1			T31	1		T42	3		T54	4
all_pins[3]	transitions[0x0=>0x1]	76	1			T31	1		T42	3		T54	3
all_pins[3]	transitions[0x1=>0x0]	77	1			T42	1		T57	2		T54	1
all_pins[4]	values[0x0]	1008053	1			T2	7313		T3	4		T4	3
all_pins[4]	values[0x1]	94	1			T42	1		T57	2		T54	2
all_pins[4]	transitions[0x0=>0x1]	68	1			T57	2		T186	1		T212	1
all_pins[4]	transitions[0x1=>0x0]	99	1			T31	1		T42	1		T54	3
all_pins[5]	values[0x0]	1008022	1			T2	7313		T3	4		T4	3
all_pins[5]	values[0x1]	125	1			T31	1		T42	2		T54	5
all_pins[5]	transitions[0x0=>0x1]	98	1			T31	1		T42	2		T54	5
all_pins[5]	transitions[0x1=>0x0]	86	1			T31	2		T42	1		T124	2
all_pins[6]	values[0x0]	1008034	1			T2	7313		T3	4		T4	3
all_pins[6]	values[0x1]	113	1			T31	2		T42	1		T124	2
all_pins[6]	transitions[0x0=>0x1]	89	1			T31	2		T42	1		T124	2
all_pins[6]	transitions[0x1=>0x0]	35321	1			T2	322		T4	1		T7	1
all_pins[7]	values[0x0]	972802	1			T2	6991		T3	4		T4	2
all_pins[7]	values[0x1]	35345	1			T2	322		T4	1		T7	1
all_pins[7]	transitions[0x0=>0x1]	35325	1			T2	322		T4	1		T7	1
all_pins[7]	transitions[0x1=>0x0]	85	1			T54	1		T124	1		T49	2
all_pins[8]	values[0x0]	1008042	1			T2	7313		T3	4		T4	3
all_pins[8]	values[0x1]	105	1			T42	1		T54	1		T186	1
all_pins[8]	transitions[0x0=>0x1]	66	1			T42	1		T186	1		T49	2
all_pins[8]	transitions[0x1=>0x0]	780524	1			T2	6781		T3	1		T4	1
all_pins[9]	values[0x0]	227584	1			T2	532		T3	3		T4	2
all_pins[9]	values[0x1]	780563	1			T2	6781		T3	1		T4	1
all_pins[9]	transitions[0x0=>0x1]	780539	1			T2	6781		T3	1		T4	1
all_pins[9]	transitions[0x1=>0x0]	63	1			T42	1		T54	2		T186	1
all_pins[10]	values[0x0]	1008060	1			T2	7313		T3	4		T4	3
all_pins[10]	values[0x1]	87	1			T42	1		T54	3		T186	1
all_pins[10]	transitions[0x0=>0x1]	57	1			T42	1		T54	1		T186	1
all_pins[10]	transitions[0x1=>0x0]	1001327	1			T2	7304		T3	4		T4	2
all_pins[11]	values[0x0]	6790	1			T2	9		T4	1		T5	19
all_pins[11]	values[0x1]	1001357	1			T2	7304		T3	4		T4	2
all_pins[11]	transitions[0x0=>0x1]	1001302	1			T2	7304		T3	4		T4	2
all_pins[11]	transitions[0x1=>0x0]	62	1			T49	1		T137	1		T70	2
all_pins[12]	values[0x0]	1008030	1			T2	7313		T3	4		T4	3
all_pins[12]	values[0x1]	117	1			T18	1		T211	1		T54	1
all_pins[12]	transitions[0x0=>0x1]	96	1			T18	1		T211	1		T54	1
all_pins[12]	transitions[0x1=>0x0]	88	1			T42	1		T54	3		T186	3
all_pins[13]	values[0x0]	1008038	1			T2	7313		T3	4		T4	3
all_pins[13]	values[0x1]	109	1			T42	1		T54	3		T186	4
all_pins[13]	transitions[0x0=>0x1]	84	1			T42	1		T54	3		T186	4
all_pins[13]	transitions[0x1=>0x0]	73	1			T42	1		T54	4		T186	1
all_pins[14]	values[0x0]	1008049	1			T2	7313		T3	4		T4	3
all_pins[14]	values[0x1]	98	1			T42	1		T54	4		T186	1
all_pins[14]	transitions[0x0=>0x1]	66	1			T42	1		T54	2		T124	2
all_pins[14]	transitions[0x1=>0x0]	871197	1			T2	6738		T3	3		T4	1