Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	470	1			T31	4		T42	7		T54	11
all_values[1]	470	1			T31	4		T42	7		T54	11
all_values[2]	470	1			T31	4		T42	7		T54	11
all_values[3]	470	1			T31	4		T42	7		T54	11
all_values[4]	470	1			T31	4		T42	7		T54	11
all_values[5]	470	1			T31	4		T42	7		T54	11
all_values[6]	470	1			T31	4		T42	7		T54	11
all_values[7]	470	1			T31	4		T42	7		T54	11
all_values[8]	470	1			T31	4		T42	7		T54	11
all_values[9]	470	1			T31	4		T42	7		T54	11
all_values[10]	470	1			T31	4		T42	7		T54	11
all_values[11]	470	1			T31	4		T42	7		T54	11
all_values[12]	470	1			T31	4		T42	7		T54	11
all_values[13]	470	1			T31	4		T42	7		T54	11
all_values[14]	470	1			T31	4		T42	7		T54	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3723

1

T31

21

T42

48

T54

59

auto[1]

3327

1

T31

39

T42

57

T54

106

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T31

17

T42

10

T54

20

auto[1]

5870

1

T31

43

T42

95

T54

145

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4206

1

T31

37

T42

53

T54

100

auto[1]

2844

1

T31

23

T42

52

T54

65

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	45	1			T124	2		T137	1		T224	2
all_values[0]	auto[0]	auto[0]	auto[1]	99	1			T42	3		T54	4		T186	2
all_values[0]	auto[0]	auto[1]	auto[0]	41	1			T31	1		T42	1		T54	1
all_values[0]	auto[0]	auto[1]	auto[1]	102	1			T31	2		T42	2		T54	2
all_values[0]	auto[1]	auto[0]	auto[1]	100	1			T31	1		T42	1		T54	1
all_values[0]	auto[1]	auto[1]	auto[1]	83	1			T54	3		T186	3		T49	2
all_values[1]	auto[0]	auto[0]	auto[0]	48	1			T31	1		T186	4		T124	1
all_values[1]	auto[0]	auto[0]	auto[1]	98	1			T42	1		T54	4		T186	1
all_values[1]	auto[0]	auto[1]	auto[0]	23	1			T31	3		T137	1		T69	1
all_values[1]	auto[0]	auto[1]	auto[1]	102	1			T42	1		T54	2		T186	1
all_values[1]	auto[1]	auto[0]	auto[1]	106	1			T42	1		T54	2		T186	1
all_values[1]	auto[1]	auto[1]	auto[1]	93	1			T42	4		T54	3		T124	1
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T137	1		T70	2		T108	1
all_values[2]	auto[0]	auto[0]	auto[1]	102	1			T54	1		T186	1		T124	1
all_values[2]	auto[0]	auto[1]	auto[0]	46	1			T31	1		T54	1		T186	3
all_values[2]	auto[0]	auto[1]	auto[1]	104	1			T31	1		T42	4		T54	3
all_values[2]	auto[1]	auto[0]	auto[1]	98	1			T31	1		T54	3		T124	1
all_values[2]	auto[1]	auto[1]	auto[1]	80	1			T31	1		T42	3		T54	3
all_values[3]	auto[0]	auto[0]	auto[0]	51	1			T49	2		T224	1		T70	1
all_values[3]	auto[0]	auto[0]	auto[1]	102	1			T31	1		T42	2		T54	1
all_values[3]	auto[0]	auto[1]	auto[0]	31	1			T42	1		T49	2		T137	1
all_values[3]	auto[0]	auto[1]	auto[1]	100	1			T31	1		T54	3		T186	2
all_values[3]	auto[1]	auto[0]	auto[1]	102	1			T31	1		T42	2		T186	2
all_values[3]	auto[1]	auto[1]	auto[1]	84	1			T31	1		T42	2		T54	7
all_values[4]	auto[0]	auto[0]	auto[0]	61	1			T124	2		T49	2		T224	4
all_values[4]	auto[0]	auto[0]	auto[1]	95	1			T31	1		T42	2		T54	2
all_values[4]	auto[0]	auto[1]	auto[0]	39	1			T31	2		T54	1		T186	1
all_values[4]	auto[0]	auto[1]	auto[1]	100	1			T42	1		T54	4		T137	4
all_values[4]	auto[1]	auto[0]	auto[1]	97	1			T42	2		T69	2		T224	1
all_values[4]	auto[1]	auto[1]	auto[1]	78	1			T31	1		T42	2		T54	4
all_values[5]	auto[0]	auto[0]	auto[0]	37	1			T42	2		T124	1		T137	5
all_values[5]	auto[0]	auto[0]	auto[1]	95	1			T31	1		T54	2		T186	3
all_values[5]	auto[0]	auto[1]	auto[0]	25	1			T42	2		T54	1		T186	1
all_values[5]	auto[0]	auto[1]	auto[1]	105	1			T31	1		T42	1		T54	5
all_values[5]	auto[1]	auto[0]	auto[1]	108	1			T31	1		T42	1		T186	2
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T31	1		T42	1		T54	3
all_values[6]	auto[0]	auto[0]	auto[0]	53	1			T54	1		T186	1		T124	2
all_values[6]	auto[0]	auto[0]	auto[1]	111	1			T42	2		T54	2		T186	3
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T31	1		T54	4		T224	1
all_values[6]	auto[0]	auto[1]	auto[1]	95	1			T31	1		T42	1		T54	1
all_values[6]	auto[1]	auto[0]	auto[1]	95	1			T42	2		T54	2		T186	3
all_values[6]	auto[1]	auto[1]	auto[1]	90	1			T31	2		T42	2		T54	1
all_values[7]	auto[0]	auto[0]	auto[0]	38	1			T42	1		T54	4		T224	1
all_values[7]	auto[0]	auto[0]	auto[1]	97	1			T31	1		T42	1		T186	1
all_values[7]	auto[0]	auto[1]	auto[0]	33	1			T42	2		T54	4		T69	1
all_values[7]	auto[0]	auto[1]	auto[1]	95	1			T54	1		T186	2		T137	2
all_values[7]	auto[1]	auto[0]	auto[1]	111	1			T42	1		T54	1		T186	1
all_values[7]	auto[1]	auto[1]	auto[1]	96	1			T31	3		T42	2		T54	1
all_values[8]	auto[0]	auto[0]	auto[0]	43	1			T56	4		T231	1		T108	4
all_values[8]	auto[0]	auto[0]	auto[1]	104	1			T42	1		T54	5		T186	2
all_values[8]	auto[0]	auto[1]	auto[0]	23	1			T31	1		T54	1		T69	1
all_values[8]	auto[0]	auto[1]	auto[1]	112	1			T31	1		T42	2		T54	3
all_values[8]	auto[1]	auto[0]	auto[1]	89	1			T31	1		T42	1		T124	1
all_values[8]	auto[1]	auto[1]	auto[1]	99	1			T31	1		T42	3		T54	2
all_values[9]	auto[0]	auto[0]	auto[0]	42	1			T49	2		T69	1		T231	4
all_values[9]	auto[0]	auto[0]	auto[1]	99	1			T31	1		T42	3		T54	1
all_values[9]	auto[0]	auto[1]	auto[0]	28	1			T31	1		T54	1		T49	2
all_values[9]	auto[0]	auto[1]	auto[1]	106	1			T54	5		T186	1		T124	2
all_values[9]	auto[1]	auto[0]	auto[1]	101	1			T31	1		T42	1		T54	2
all_values[9]	auto[1]	auto[1]	auto[1]	94	1			T31	1		T42	3		T54	2
all_values[10]	auto[0]	auto[0]	auto[0]	37	1			T124	1		T224	1		T56	2
all_values[10]	auto[0]	auto[0]	auto[1]	117	1			T31	1		T42	1		T54	5
all_values[10]	auto[0]	auto[1]	auto[0]	36	1			T54	1		T186	2		T124	1
all_values[10]	auto[0]	auto[1]	auto[1]	98	1			T31	2		T42	3		T54	2
all_values[10]	auto[1]	auto[0]	auto[1]	104	1			T42	1		T186	1		T124	1
all_values[10]	auto[1]	auto[1]	auto[1]	78	1			T31	1		T42	2		T54	3
all_values[11]	auto[0]	auto[0]	auto[0]	34	1			T231	1		T232	1		T233	1
all_values[11]	auto[0]	auto[0]	auto[1]	100	1			T31	2		T42	1		T54	1
all_values[11]	auto[0]	auto[1]	auto[0]	31	1			T31	1		T56	2		T111	1
all_values[11]	auto[0]	auto[1]	auto[1]	107	1			T42	1		T54	3		T186	4
all_values[11]	auto[1]	auto[0]	auto[1]	99	1			T42	3		T54	3		T186	1
all_values[11]	auto[1]	auto[1]	auto[1]	99	1			T31	1		T42	2		T54	4
all_values[12]	auto[0]	auto[0]	auto[0]	44	1			T31	1		T124	2		T56	2
all_values[12]	auto[0]	auto[0]	auto[1]	106	1			T42	1		T54	2		T186	1
all_values[12]	auto[0]	auto[1]	auto[0]	41	1			T31	3		T186	1		T137	2
all_values[12]	auto[0]	auto[1]	auto[1]	98	1			T42	2		T54	5		T186	2
all_values[12]	auto[1]	auto[0]	auto[1]	93	1			T42	3		T54	1		T186	1
all_values[12]	auto[1]	auto[1]	auto[1]	88	1			T42	1		T54	3		T186	2
all_values[13]	auto[0]	auto[0]	auto[0]	57	1			T186	1		T137	3		T69	1
all_values[13]	auto[0]	auto[0]	auto[1]	97	1			T31	1		T42	3		T54	4
all_values[13]	auto[0]	auto[1]	auto[0]	38	1			T49	4		T137	5		T69	3
all_values[13]	auto[0]	auto[1]	auto[1]	84	1			T31	1		T42	1		T54	2
all_values[13]	auto[1]	auto[0]	auto[1]	93	1			T31	1		T42	2		T54	2
all_values[13]	auto[1]	auto[1]	auto[1]	101	1			T31	1		T42	1		T54	3
all_values[14]	auto[0]	auto[0]	auto[0]	61	1			T137	1		T70	1		T102	1
all_values[14]	auto[0]	auto[0]	auto[1]	114	1			T31	1		T42	2		T54	1
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T31	1		T42	1		T102	1
all_values[14]	auto[0]	auto[1]	auto[1]	82	1			T42	1		T54	4		T186	3
all_values[14]	auto[1]	auto[0]	auto[1]	100	1			T31	2		T42	1		T54	2
all_values[14]	auto[1]	auto[1]	auto[1]	85	1			T42	2		T54	4		T186	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal