Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

169179

1

T4

92

T10

91

T26

431

ack

15398

1

T1

1

T2

14

T3

36

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	676	1			T25	1		T26	1		T59	2
high	37797	1			T2	2		T3	4		T4	15
med	68745	1			T2	2		T3	3		T4	33
sml	76638	1			T1	1		T2	10		T3	29
all_zero	721	1			T4	2		T10	1		T26	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91830

1

T2

7

T3

13

T4

47

auto[1]

92747

1

T1

1

T2

7

T3

23

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126916

1

T1

1

T2

14

T3

27

auto[1]

57661

1

T3

9

T4

32

T10

27

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176436

1

T1

1

T2

7

T3

14

auto[1]

8141

1

T2

7

T3

22

T25

25

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174058

1

T2

7

T3

22

T4

92

auto[1]

10519

1

T1

1

T2

7

T3

14

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175041

1

T1

1

T2

7

T3

23

auto[1]

9536

1

T2

7

T3

13

T4

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91830

1

T2

7

T3

13

T4

47

auto[1]

92747

1

T1

1

T2

7

T3

23

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126916

1

T1

1

T2

14

T3

27

auto[1]

57661

1

T3

9

T4

32

T10

27

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176436

1

T1

1

T2

7

T3

14

auto[1]

8141

1

T2

7

T3

22

T25

25

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174058

1

T2

7

T3

22

T4

92

auto[1]

10519

1

T1

1

T2

7

T3

14

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175041

1

T1

1

T2

7

T3

23

auto[1]

9536

1

T2

7

T3

13

T4

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T80

1

T257

1

T258

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T86

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T259

1

T260

2

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

293

1

T26

1

T72

1

T261

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

152

1

T26

1

T72

1

T144

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

145

1

T38

1

T144

1

T80

5

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

590

1

T26

1

T59

4

T72

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

271

1

T59

1

T72

1

T262

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

269

1

T26

1

T144

1

T138

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

593

1

T26

2

T59

3

T72

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

254

1

T59

2

T72

2

T262

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

298

1

T59

2

T72

1

T261

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T109

1

T263

1

T77

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

13

1

T80

1

T264

1

T265

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T266

1

T228

1

T267

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	53759	1			T4	31		T10	29		T26	142
write_address_byte	10519	1			T1	1		T2	7		T3	14
read_with_ack	2364	1			T3	9		T25	11		T26	2
read_with_nack	5777	1			T2	7		T3	13		T25	14
stop_byte	9536	1			T2	7		T3	13		T4	1
write_address_byte_nak	5248	1			T26	11		T59	18		T34	10
data_byte_nack	169179	1			T4	92		T10	91		T26	431
stop_byte_nack	5745	1			T4	1		T10	13		T26	7
nakok_byte_nack	84952	1			T4	45		T10	45		T26	225
nakok_addr_byte_nack	2619	1			T26	7		T59	9		T34	5