Unified Coverage Report :: Group :: tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	85.71	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_rd_wr_cg	85.71	1	100	1	64	64

---

Group Instance : i2c_rd_wr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance i2c_rd_wr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	24	4	20	83.33

Variables for Group Instance i2c_rd_wr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
address_match	2	0	2	100.00	100	1	1	2
cp_address_match	4	0	4	100.00	100	1	1	0
cp_read_byte	5	1	4	80.00	100	1	1	0
cp_write_byte	5	1	4	80.00	100	1	1	0
ip_mode_cp	2	0	2	100.00	100	1	1	0

Crosses for Group Instance i2c_rd_wr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_address_match_x_ip_mode	4	0	4	100.00	100	1	1	0
cross_write_byte_x_ip_mode	10	2	8	80.00	100	1	1	0
cross_read_byte_x_ip_mode	10	2	8	80.00	100	1	1	0

Summary for Variable address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for address_match

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5765228

1

T5

493

T6

9099

T8

4475

auto[1]

16232284

1

T1

370

T2

25868

T3

26098

---

Summary for Variable cp_address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_address_match

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_addr_no_match	2241886	1			T6	2316		T8	2582		T9	12927
read_addr_match	11664817	1			T1	349		T2	25849		T3	25379
write_addr_no_match	3314432	1			T5	481		T6	2629		T8	1873
write_addr_match	4467878	1			T4	2252		T5	5		T6	74

---

Summary for Variable cp_read_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_read_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	2817705	1			T1	82		T2	5531		T3	5351
med	5369134	1			T1	129		T2	9800		T3	9872
low	5577529	1			T1	124		T2	10354		T3	9941
all_zero	142335	1			T1	14		T2	164		T3	215

---

Summary for Variable cp_write_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_write_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	1584659	1			T4	551		T5	90		T6	617
med	3031507	1			T4	637		T5	186		T6	1014
low	3086370	1			T4	1005		T5	189		T6	1027
all_zero	79774	1			T4	59		T5	21		T6	45

---

Summary for Variable ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for ip_mode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

device

6152259

1

T3

659

T5

512

T6

9270

host

15845253

1

T1

370

T2

25868

T3

25439

---

Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins

address_match

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

device

5765149

1

T5

493

T6

9099

T8

4475

auto[0]

host

79

1

T181

1

T96

2

T216

1

auto[1]

device

387110

1

T3

659

T5

19

T6

171

auto[1]

host

15845174

1

T1

370

T2

25868

T3

25439

---

Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	708082	1			T5	90		T6	617		T8	405
high	host	876577	1			T4	551		T10	392		T26	2055
med	device	1366130	1			T5	186		T6	1014		T8	756
med	host	1665377	1			T4	637		T10	1401		T26	4309
low	device	1399060	1			T5	189		T6	1027		T8	773
low	host	1687310	1			T4	1005		T10	793		T26	4234
all_zero	device	35645	1			T5	21		T6	45		T8	12
all_zero	host	44129	1			T4	59		T10	26		T26	98

---

Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	708082	1			T5	90		T6	617		T8	405
high	host	876577	1			T4	551		T10	392		T26	2055
med	device	1366130	1			T5	186		T6	1014		T8	756
med	host	1665377	1			T4	637		T10	1401		T26	4309
low	device	1399060	1			T5	189		T6	1027		T8	773
low	host	1687310	1			T4	1005		T10	793		T26	4234
all_zero	device	35645	1			T5	21		T6	45		T8	12
all_zero	host	44129	1			T4	59		T10	26		T26	98