Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47407071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11750208

1

T1

4376

T2

8904

T3

5300

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58405333	1			T1	16693		T2	18365		T3	17139
values[0x0]	375325	1			T1	169		T2	84		T3	472
values[0x1]	376621	1			T1	178		T2	73		T3	452

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33897843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25259436

1

T1

7998

T2

10991

T3

8873

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	237584	1			T1	79		T3	81		T9	81
valid_sources[0x01]	207748	1			T1	55		T3	73		T9	62
valid_sources[0x02]	215559	1			T1	60		T3	91		T6	4
valid_sources[0x03]	209964	1			T1	79		T3	101		T9	56
valid_sources[0x04]	198456	1			T1	82		T3	69		T6	1
valid_sources[0x05]	458373	1			T1	67		T3	78		T9	85
valid_sources[0x06]	214260	1			T1	69		T3	63		T9	70
valid_sources[0x07]	201079	1			T1	67		T3	78		T9	45
valid_sources[0x08]	201961	1			T1	49		T3	98		T9	40
valid_sources[0x09]	203184	1			T1	59		T3	93		T9	76
valid_sources[0x0a]	211039	1			T1	73		T3	82		T9	110
valid_sources[0x0b]	194152	1			T1	73		T3	42		T9	48
valid_sources[0x0c]	289404	1			T1	71		T3	76		T9	73
valid_sources[0x0d]	209200	1			T1	56		T3	46		T4	104
valid_sources[0x0e]	226957	1			T1	75		T3	82		T6	1
valid_sources[0x0f]	209320	1			T1	51		T3	55		T5	1
valid_sources[0x10]	226134	1			T1	72		T3	48		T4	28
valid_sources[0x11]	198676	1			T1	67		T3	78		T4	7
valid_sources[0x12]	202005	1			T1	65		T3	62		T6	10
valid_sources[0x13]	226486	1			T1	68		T3	45		T9	38
valid_sources[0x14]	341937	1			T1	73		T3	81		T4	90
valid_sources[0x15]	214325	1			T1	65		T3	81		T9	80
valid_sources[0x16]	330383	1			T1	73		T3	66		T6	4
valid_sources[0x17]	211870	1			T1	50		T3	63		T4	94
valid_sources[0x18]	200624	1			T1	69		T3	68		T6	3
valid_sources[0x19]	298153	1			T1	68		T2	1		T3	76
valid_sources[0x1a]	208797	1			T1	45		T3	81		T9	58
valid_sources[0x1b]	223426	1			T1	63		T3	66		T9	63
valid_sources[0x1c]	197702	1			T1	66		T3	73		T4	36
valid_sources[0x1d]	215675	1			T1	66		T3	83		T9	76
valid_sources[0x1e]	231575	1			T1	60		T3	83		T4	3
valid_sources[0x1f]	209825	1			T1	68		T3	80		T9	46
valid_sources[0x20]	231126	1			T1	50		T3	90		T6	10
valid_sources[0x21]	221467	1			T1	59		T3	102		T9	50
valid_sources[0x22]	209288	1			T1	69		T3	64		T4	152
valid_sources[0x23]	201892	1			T1	79		T3	75		T9	50
valid_sources[0x24]	308737	1			T1	63		T3	85		T9	76
valid_sources[0x25]	219468	1			T1	65		T3	58		T6	1
valid_sources[0x26]	190583	1			T1	67		T3	69		T5	1
valid_sources[0x27]	216982	1			T1	81		T3	94		T4	81
valid_sources[0x28]	214752	1			T1	62		T3	51		T4	40
valid_sources[0x29]	188821	1			T1	64		T3	66		T6	1
valid_sources[0x2a]	211712	1			T1	66		T2	1		T3	48
valid_sources[0x2b]	205548	1			T1	60		T3	73		T4	5
valid_sources[0x2c]	188821	1			T1	59		T3	71		T6	1
valid_sources[0x2d]	233754	1			T1	53		T3	83		T9	50
valid_sources[0x2e]	203217	1			T1	50		T3	58		T4	22
valid_sources[0x2f]	203329	1			T1	71		T3	51		T9	69
valid_sources[0x30]	344430	1			T1	66		T3	65		T5	2
valid_sources[0x31]	231835	1			T1	58		T3	63		T5	1
valid_sources[0x32]	204442	1			T1	71		T3	70		T4	24
valid_sources[0x33]	224004	1			T1	63		T3	86		T4	43
valid_sources[0x34]	220750	1			T1	81		T3	70		T5	3
valid_sources[0x35]	202700	1			T1	66		T3	62		T9	77
valid_sources[0x36]	203207	1			T1	53		T3	83		T6	6
valid_sources[0x37]	211899	1			T1	63		T3	96		T9	42
valid_sources[0x38]	221829	1			T1	76		T3	49		T9	105
valid_sources[0x39]	223813	1			T1	69		T3	54		T6	3
valid_sources[0x3a]	219254	1			T1	68		T3	59		T4	76
valid_sources[0x3b]	206850	1			T1	55		T3	79		T9	114
valid_sources[0x3c]	200868	1			T1	66		T3	82		T4	14
valid_sources[0x3d]	213487	1			T1	70		T3	90		T6	5
valid_sources[0x3e]	205367	1			T1	61		T3	63		T6	6
valid_sources[0x3f]	236779	1			T1	63		T3	57		T6	1
valid_sources[0x40]	202951	1			T1	54		T2	1		T3	83
valid_sources[0x41]	199353	1			T1	58		T3	64		T6	1
valid_sources[0x42]	198666	1			T1	58		T3	74		T4	14
valid_sources[0x43]	357973	1			T1	55		T2	1		T3	51
valid_sources[0x44]	212676	1			T1	70		T3	54		T6	7
valid_sources[0x45]	221848	1			T1	71		T3	70		T6	1
valid_sources[0x46]	219595	1			T1	54		T3	71		T6	7
valid_sources[0x47]	209639	1			T1	58		T3	72		T4	137
valid_sources[0x48]	257704	1			T1	77		T3	70		T6	1
valid_sources[0x49]	218747	1			T1	56		T3	75		T4	10
valid_sources[0x4a]	225168	1			T1	78		T2	1		T3	82
valid_sources[0x4b]	210465	1			T1	73		T3	57		T4	21
valid_sources[0x4c]	216570	1			T1	78		T3	73		T9	57
valid_sources[0x4d]	190199	1			T1	58		T3	49		T9	47
valid_sources[0x4e]	191765	1			T1	77		T3	93		T9	51
valid_sources[0x4f]	204858	1			T1	62		T3	54		T9	82
valid_sources[0x50]	210457	1			T1	52		T3	60		T4	16
valid_sources[0x51]	277316	1			T1	70		T3	78		T9	69
valid_sources[0x52]	212842	1			T1	69		T3	76		T9	62
valid_sources[0x53]	218079	1			T1	61		T3	85		T9	57
valid_sources[0x54]	193106	1			T1	78		T3	62		T4	8
valid_sources[0x55]	216570	1			T1	69		T2	1		T3	74
valid_sources[0x56]	275104	1			T1	79		T3	87		T6	7
valid_sources[0x57]	217073	1			T1	69		T3	95		T6	7
valid_sources[0x58]	216810	1			T1	72		T3	77		T6	3
valid_sources[0x59]	213803	1			T1	58		T3	89		T6	3
valid_sources[0x5a]	204860	1			T1	61		T3	80		T6	10
valid_sources[0x5b]	224626	1			T1	65		T2	1		T3	58
valid_sources[0x5c]	203191	1			T1	55		T3	78		T9	54
valid_sources[0x5d]	217526	1			T1	64		T3	72		T9	47
valid_sources[0x5e]	222503	1			T1	73		T3	84		T4	66
valid_sources[0x5f]	211653	1			T1	73		T3	82		T6	11
valid_sources[0x60]	204274	1			T1	73		T3	60		T9	63
valid_sources[0x61]	202757	1			T1	66		T3	54		T6	5
valid_sources[0x62]	214232	1			T1	81		T2	1		T3	87
valid_sources[0x63]	208036	1			T1	60		T3	70		T9	73
valid_sources[0x64]	217408	1			T1	90		T3	84		T6	6
valid_sources[0x65]	201030	1			T1	63		T2	1		T3	72
valid_sources[0x66]	217653	1			T1	71		T3	61		T9	59
valid_sources[0x67]	182347	1			T1	63		T2	1		T3	86
valid_sources[0x68]	199994	1			T1	76		T3	57		T4	7
valid_sources[0x69]	213583	1			T1	70		T3	54		T6	1
valid_sources[0x6a]	198153	1			T1	73		T3	52		T9	36
valid_sources[0x6b]	211135	1			T1	95		T2	6		T3	77
valid_sources[0x6c]	206596	1			T1	72		T3	78		T6	3
valid_sources[0x6d]	193473	1			T1	63		T3	67		T4	30
valid_sources[0x6e]	309656	1			T1	82		T3	75		T6	11
valid_sources[0x6f]	511948	1			T1	70		T3	74		T6	1
valid_sources[0x70]	185764	1			T1	49		T3	56		T9	59
valid_sources[0x71]	196277	1			T1	56		T2	1		T3	67
valid_sources[0x72]	195429	1			T1	68		T2	1		T3	86
valid_sources[0x73]	250972	1			T1	64		T3	67		T4	63
valid_sources[0x74]	194331	1			T1	64		T3	57		T6	10
valid_sources[0x75]	245315	1			T1	68		T3	66		T6	4
valid_sources[0x76]	198323	1			T1	54		T2	1		T3	69
valid_sources[0x77]	211173	1			T1	64		T3	71		T9	44
valid_sources[0x78]	236820	1			T1	53		T3	65		T4	38
valid_sources[0x79]	206146	1			T1	71		T3	80		T9	74
valid_sources[0x7a]	222776	1			T1	58		T3	56		T6	13
valid_sources[0x7b]	207322	1			T1	72		T2	1		T3	75
valid_sources[0x7c]	199410	1			T1	55		T2	1		T3	65
valid_sources[0x7d]	222883	1			T1	55		T3	79		T9	69
valid_sources[0x7e]	187805	1			T1	46		T3	59		T9	57
valid_sources[0x7f]	199469	1			T1	81		T3	66		T6	9
valid_sources[0x80]	202589	1			T1	60		T3	75		T9	95

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11383073

1

T1

4239

T2

8775

T3

4739

values[0x0]

all_enables

biggest_size

211476

1

T1

79

T2

70

T3

310

values[0x1]

all_enables

biggest_size

155659

1

T1

58

T2

59

T3

251