Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	87.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_target_cg	75.00	1	100	1	64	64
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	2	6	75.00

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	2	6	75.00	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	2	6	75.00

User Defined Bins for B2B_txn_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
write_after_read_same_addr	0	1	1
read_after_write_same_addr	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	41	1			T225	1		T273	1		T274	1
b2b_read_same_addr	212	1			T8	1		T17	1		T11	1
write_after_read_different_addr	46	1			T275	1		T197	1		T69	1
read_after_write_different_addr	52	1			T6	1		T276	1		T277	1
b2b_write_different_addr	49	1			T21	1		T150	1		T278	1
b2b_write_same_addr	238	1			T9	1		T20	1		T22	1

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	3616	1			T2	2		T3	8		T10	3
b2b_read_same_addr	266	1			T26	1		T34	4		T40	1
write_after_read_different_addr	3602	1			T2	4		T3	9		T10	3
write_after_read_same_addr	65	1			T25	1		T59	1		T68	2
read_after_write_different_addr	3622	1			T2	3		T3	8		T10	2
read_after_write_same_addr	57	1			T80	1		T86	1		T31	1
b2b_write_different_addr	3541	1			T2	4		T3	10		T10	4
b2b_write_same_addr	275	1			T26	3		T34	1		T27	1