Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	378549223	0	0	0
ctrl_rd_A	378549223	2718	0	0
host_fifo_config_rd_A	378549223	5799	0	0
host_nack_handler_timeout_rd_A	378549223	1659	0	0
host_timeout_ctrl_rd_A	378549223	1498	0	0
intr_enable_rd_A	378549223	3824	0	0
ovrd_rd_A	378549223	2676	0	0
target_fifo_config_rd_A	378549223	1652	0	0
target_id_rd_A	378549223	1974	0	0
target_timeout_ctrl_rd_A	378549223	1733	0	0
timeout_ctrl_rd_A	378549223	1854	0	0
timing0_rd_A	378549223	1658	0	0
timing1_rd_A	378549223	1770	0	0
timing2_rd_A	378549223	1702	0	0
timing3_rd_A	378549223	1690	0	0
timing4_rd_A	378549223	1624	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	2718	0	0
T94	8507	8	0	0
T95	7864	11	0	0
T96	8372	181	0	0
T97	2708	16	0	0
T98	15545	369	0	0
T99	9298	14	0	0
T100	2228	30	0	0
T101	2271	13	0	0
T102	3336	3	0	0
T103	31990	200	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	5799	0	0
T15	113419	0	0	0
T21	28564	0	0	0
T22	130390	0	0	0
T23	41145	0	0	0
T29	123861	0	0	0
T33	0	247	0	0
T34	58103	0	0	0
T40	115607	0	0	0
T54	0	150	0	0
T59	274474	41	0	0
T68	198148	0	0	0
T80	0	534	0	0
T104	0	205	0	0
T105	0	116	0	0
T106	0	144	0	0
T107	0	80	0	0
T108	0	196	0	0
T109	0	173	0	0
T110	189109	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1659	0	0
T94	8507	36	0	0
T95	7864	16	0	0
T96	8372	57	0	0
T97	2708	10	0	0
T98	15545	89	0	0
T99	9298	8	0	0
T100	2228	7	0	0
T101	2271	13	0	0
T102	3336	8	0	0
T103	31990	216	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1498	0	0
T94	8507	29	0	0
T95	7864	16	0	0
T96	8372	47	0	0
T97	2708	11	0	0
T98	15545	87	0	0
T99	9298	22	0	0
T100	2228	7	0	0
T101	2271	9	0	0
T102	3336	32	0	0
T103	31990	228	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	3824	0	0
T33	0	10	0	0
T54	0	25	0	0
T80	197866	12	0	0
T85	12862	0	0	0
T86	59720	0	0	0
T87	1328	0	0	0
T88	15645	0	0	0
T89	61199	0	0	0
T90	427174	0	0	0
T91	65158	0	0	0
T92	181561	0	0	0
T93	268093	0	0	0
T94	0	18	0	0
T111	0	26	0	0
T112	0	22	0	0
T113	0	36	0	0
T114	0	3	0	0
T115	0	22	0	0
T116	0	22	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	2676	0	0
T65	2958	63	0	0
T66	1083	0	0	0
T117	0	28	0	0
T118	0	34	0	0
T119	0	21	0	0
T120	0	29	0	0
T121	0	37	0	0
T122	0	57	0	0
T123	0	36	0	0
T124	0	32	0	0
T125	0	31	0	0
T126	125254	0	0	0
T127	12432	0	0	0
T128	139493	0	0	0
T129	248184	0	0	0
T130	25033	0	0	0
T131	37622	0	0	0
T132	39160	0	0	0
T133	35993	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1652	0	0
T94	8507	11	0	0
T95	7864	36	0	0
T96	8372	46	0	0
T97	2708	17	0	0
T98	15545	114	0	0
T99	9298	11	0	0
T100	2228	10	0	0
T101	2271	3	0	0
T102	3336	6	0	0
T103	31990	231	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1974	0	0
T94	8507	15	0	0
T95	7864	20	0	0
T96	8372	124	0	0
T97	2708	27	0	0
T98	15545	155	0	0
T99	9298	6	0	0
T100	2228	5	0	0
T101	2271	3	0	0
T102	3336	12	0	0
T103	31990	240	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1733	0	0
T94	8507	19	0	0
T95	7864	30	0	0
T96	8372	51	0	0
T97	2708	17	0	0
T98	15545	99	0	0
T99	9298	9	0	0
T100	2228	11	0	0
T101	2271	6	0	0
T102	3336	43	0	0
T103	31990	221	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1854	0	0
T94	8507	32	0	0
T95	7864	5	0	0
T96	8372	82	0	0
T97	2708	9	0	0
T98	15545	171	0	0
T99	9298	20	0	0
T100	2228	13	0	0
T101	2271	8	0	0
T102	3336	25	0	0
T103	31990	249	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1658	0	0
T94	8507	19	0	0
T95	7864	10	0	0
T96	8372	33	0	0
T97	2708	11	0	0
T98	15545	94	0	0
T99	9298	33	0	0
T100	2228	14	0	0
T101	2271	14	0	0
T102	3336	19	0	0
T103	31990	220	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1770	0	0
T94	8507	22	0	0
T95	7864	16	0	0
T96	8372	54	0	0
T97	2708	7	0	0
T98	15545	112	0	0
T99	9298	33	0	0
T100	2228	6	0	0
T101	2271	5	0	0
T102	3336	9	0	0
T103	31990	233	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1702	0	0
T94	8507	10	0	0
T95	7864	26	0	0
T96	8372	51	0	0
T97	2708	8	0	0
T98	15545	88	0	0
T99	9298	31	0	0
T100	2228	10	0	0
T101	2271	6	0	0
T102	3336	14	0	0
T103	31990	229	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1690	0	0
T94	8507	18	0	0
T95	7864	8	0	0
T96	8372	47	0	0
T97	2708	5	0	0
T98	15545	113	0	0
T99	9298	24	0	0
T100	2228	27	0	0
T101	2271	4	0	0
T102	3336	20	0	0
T103	31990	217	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378549223	1624	0	0
T94	8507	6	0	0
T96	8372	66	0	0
T97	2708	3	0	0
T98	15545	160	0	0
T99	9298	9	0	0
T100	2228	10	0	0
T101	2271	1	0	0
T102	3336	3	0	0
T103	31990	206	0	0
T134	2544	8	0	0