Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	345	1			T6	5		T9	5		T14	1
all_values[1]	345	1			T6	5		T9	5		T14	1
all_values[2]	345	1			T6	5		T9	5		T14	1
all_values[3]	345	1			T6	5		T9	5		T14	1
all_values[4]	345	1			T6	5		T9	5		T14	1
all_values[5]	345	1			T6	5		T9	5		T14	1
all_values[6]	345	1			T6	5		T9	5		T14	1
all_values[7]	345	1			T6	5		T9	5		T14	1
all_values[8]	345	1			T6	5		T9	5		T14	1
all_values[9]	345	1			T6	5		T9	5		T14	1
all_values[10]	345	1			T6	5		T9	5		T14	1
all_values[11]	345	1			T6	5		T9	5		T14	1
all_values[12]	345	1			T6	5		T9	5		T14	1
all_values[13]	345	1			T6	5		T9	5		T14	1
all_values[14]	345	1			T6	5		T9	5		T14	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3378

1

T6

45

T9

48

T14

15

auto[1]

1797

1

T6

30

T9

27

T10

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T6

15

T9

14

T14

15

auto[1]

4054

1

T6

60

T9

61

T10

57

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	73	1			T6	1		T14	1		T12	1
all_values[0]	auto[0]	auto[1]	155	1			T6	3		T9	2		T10	2
all_values[0]	auto[1]	auto[1]	117	1			T6	1		T9	3		T10	3
all_values[1]	auto[0]	auto[0]	65	1			T9	1		T14	1		T10	1
all_values[1]	auto[0]	auto[1]	179	1			T6	4		T9	3		T10	2
all_values[1]	auto[1]	auto[1]	101	1			T6	1		T9	1		T10	2
all_values[2]	auto[0]	auto[0]	68	1			T14	1		T12	2		T13	1
all_values[2]	auto[0]	auto[1]	167	1			T6	2		T9	3		T10	4
all_values[2]	auto[1]	auto[1]	110	1			T6	3		T9	2		T10	1
all_values[3]	auto[0]	auto[0]	99	1			T6	2		T14	1		T10	1
all_values[3]	auto[0]	auto[1]	144	1			T6	1		T9	4		T10	4
all_values[3]	auto[1]	auto[1]	102	1			T6	2		T9	1		T11	4
all_values[4]	auto[0]	auto[0]	62	1			T9	1		T14	1		T11	2
all_values[4]	auto[0]	auto[1]	166	1			T6	2		T9	2		T10	3
all_values[4]	auto[1]	auto[1]	117	1			T6	3		T9	2		T10	2
all_values[5]	auto[0]	auto[0]	68	1			T6	1		T14	1		T10	2
all_values[5]	auto[0]	auto[1]	141	1			T6	1		T9	3		T10	1
all_values[5]	auto[1]	auto[1]	136	1			T6	3		T9	2		T10	2
all_values[6]	auto[0]	auto[0]	83	1			T9	1		T14	1		T10	1
all_values[6]	auto[0]	auto[1]	137	1			T6	4		T9	1		T10	4
all_values[6]	auto[1]	auto[1]	125	1			T6	1		T9	3		T11	5
all_values[7]	auto[0]	auto[0]	77	1			T6	2		T14	1		T10	2
all_values[7]	auto[0]	auto[1]	153	1			T6	1		T9	3		T10	1
all_values[7]	auto[1]	auto[1]	115	1			T6	2		T9	2		T10	2
all_values[8]	auto[0]	auto[0]	69	1			T9	2		T14	1		T10	5
all_values[8]	auto[0]	auto[1]	142	1			T6	3		T9	1		T12	1
all_values[8]	auto[1]	auto[1]	134	1			T6	2		T9	2		T12	3
all_values[9]	auto[0]	auto[0]	63	1			T6	2		T9	1		T14	1
all_values[9]	auto[0]	auto[1]	148	1			T6	1		T9	1		T10	4
all_values[9]	auto[1]	auto[1]	134	1			T6	2		T9	3		T10	1
all_values[10]	auto[0]	auto[0]	73	1			T6	5		T9	1		T14	1
all_values[10]	auto[0]	auto[1]	151	1			T9	3		T10	2		T12	3
all_values[10]	auto[1]	auto[1]	121	1			T9	1		T10	2		T12	2
all_values[11]	auto[0]	auto[0]	89	1			T9	1		T14	1		T12	1
all_values[11]	auto[0]	auto[1]	147	1			T6	2		T9	3		T10	3
all_values[11]	auto[1]	auto[1]	109	1			T6	3		T9	1		T10	2
all_values[12]	auto[0]	auto[0]	78	1			T6	1		T14	1		T10	5
all_values[12]	auto[0]	auto[1]	161	1			T6	3		T9	4		T12	2
all_values[12]	auto[1]	auto[1]	106	1			T6	1		T9	1		T12	2
all_values[13]	auto[0]	auto[0]	74	1			T9	1		T14	1		T12	5
all_values[13]	auto[0]	auto[1]	134	1			T6	1		T9	1		T10	4
all_values[13]	auto[1]	auto[1]	137	1			T6	4		T9	3		T10	1
all_values[14]	auto[0]	auto[0]	80	1			T6	1		T9	5		T14	1
all_values[14]	auto[0]	auto[1]	132	1			T6	2		T10	2		T12	4
all_values[14]	auto[1]	auto[1]	133	1			T6	2		T10	3		T11	7