Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
52.64	40.66	40.65	90.72	0.00	42.98	99.68	53.79

Total tests in report: 163

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
45.93	45.93	39.00	39.00	37.03	37.03	93.80	93.80	0.00	0.00	41.70	41.70	95.86	95.86	14.11	14.11	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1237799039
50.82	4.89	40.20	1.19	39.22	2.18	97.02	3.23	0.00	0.00	42.84	1.13	95.86	0.00	40.63	26.53	/workspace/coverage/cover_reg_top/31.i2c_intr_test.2229221090
51.88	1.06	40.20	0.00	40.12	0.90	97.02	0.00	0.00	0.00	42.91	0.07	96.50	0.64	46.42	5.79	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2465136009
52.38	0.50	40.20	0.00	40.12	0.00	97.02	0.00	0.00	0.00	42.98	0.07	99.68	3.18	46.63	0.21	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.2871961405
52.86	0.48	40.20	0.00	40.12	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	50.00	3.37	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1480864404
53.02	0.17	40.20	0.00	40.12	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	51.16	1.16	/workspace/coverage/cover_reg_top/26.i2c_intr_test.1410047334
53.16	0.14	40.66	0.46	40.23	0.11	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	51.58	0.42	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1330697159
53.25	0.09	40.66	0.00	40.23	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	52.21	0.63	/workspace/coverage/cover_reg_top/30.i2c_intr_test.1228286163
53.33	0.08	40.66	0.00	40.23	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	52.74	0.53	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3108951328
53.37	0.05	40.66	0.00	40.23	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.05	0.32	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1256586861
53.41	0.04	40.66	0.00	40.27	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.26	0.21	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1029422195
53.44	0.03	40.66	0.00	40.38	0.11	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.37	0.11	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.1619907381
53.47	0.03	40.66	0.00	40.50	0.11	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.47	0.11	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2170628888
53.50	0.03	40.66	0.00	40.50	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.68	0.21	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3311158829
53.52	0.02	40.66	0.00	40.61	0.11	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.68	0.00	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2110262946
53.53	0.02	40.66	0.00	40.61	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.11	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3266403034
53.54	0.01	40.66	0.00	40.65	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.00	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4147923666

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2352535573
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4065803435
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3578868909
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.723617287
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1868108333
/workspace/coverage/cover_reg_top/0.i2c_intr_test.1075512683
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3956797043
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.919245559
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1078981636
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3852321890
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.698090619
/workspace/coverage/cover_reg_top/1.i2c_intr_test.1557159395
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.685937992
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.4272584288
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2515750758
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.877585648
/workspace/coverage/cover_reg_top/10.i2c_intr_test.1439151249
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2905654101
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.3688060185
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1257324804
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3222213841
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.158729871
/workspace/coverage/cover_reg_top/11.i2c_intr_test.2899925988
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1349506003
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1322963349
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.250989818
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3729567951
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.1412236105
/workspace/coverage/cover_reg_top/12.i2c_intr_test.2450291055
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1197099789
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.68685489
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3300011655
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.414096605
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2254361580
/workspace/coverage/cover_reg_top/13.i2c_intr_test.197035454
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2452963900
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.3717247160
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.982503016
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1850860047
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.389468365
/workspace/coverage/cover_reg_top/14.i2c_intr_test.1412684732
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.295245454
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2303594200
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3919110494
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1577820121
/workspace/coverage/cover_reg_top/15.i2c_intr_test.4088010776
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3294670534
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3564863405
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1319007020
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2434678966
/workspace/coverage/cover_reg_top/16.i2c_intr_test.1182337337
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1579848148
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2638580314
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2419792479
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3481516606
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2865453844
/workspace/coverage/cover_reg_top/17.i2c_intr_test.189517180
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3260312847
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.728867758
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1564981512
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.1213950948
/workspace/coverage/cover_reg_top/18.i2c_intr_test.900248181
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.898419409
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.4219970463
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3394994711
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2098228367
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2243392810
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1885602581
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2754790907
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.967307318
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3025966426
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3937135563
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1978064125
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.3853912427
/workspace/coverage/cover_reg_top/2.i2c_intr_test.3851764434
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3620709740
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3027066995
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.454036415
/workspace/coverage/cover_reg_top/20.i2c_intr_test.3032698966
/workspace/coverage/cover_reg_top/21.i2c_intr_test.3891046214
/workspace/coverage/cover_reg_top/22.i2c_intr_test.114288490
/workspace/coverage/cover_reg_top/23.i2c_intr_test.617326154
/workspace/coverage/cover_reg_top/24.i2c_intr_test.405218749
/workspace/coverage/cover_reg_top/27.i2c_intr_test.4043086185
/workspace/coverage/cover_reg_top/28.i2c_intr_test.3615045547
/workspace/coverage/cover_reg_top/29.i2c_intr_test.3744238491
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3170755602
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2653751734
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2074807788
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1986473256
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.1030849281
/workspace/coverage/cover_reg_top/3.i2c_intr_test.415259888
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2399420914
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2832269277
/workspace/coverage/cover_reg_top/32.i2c_intr_test.3364750919
/workspace/coverage/cover_reg_top/34.i2c_intr_test.50034498
/workspace/coverage/cover_reg_top/35.i2c_intr_test.1195980829
/workspace/coverage/cover_reg_top/36.i2c_intr_test.2564688230
/workspace/coverage/cover_reg_top/37.i2c_intr_test.2474765444
/workspace/coverage/cover_reg_top/38.i2c_intr_test.3894436059
/workspace/coverage/cover_reg_top/39.i2c_intr_test.3395892514
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1955851913
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.536206186
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2999894567
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.222234853
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.3140077641
/workspace/coverage/cover_reg_top/4.i2c_intr_test.3091677717
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3163126495
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.404247857
/workspace/coverage/cover_reg_top/40.i2c_intr_test.469482711
/workspace/coverage/cover_reg_top/41.i2c_intr_test.1918186366
/workspace/coverage/cover_reg_top/42.i2c_intr_test.996763925
/workspace/coverage/cover_reg_top/43.i2c_intr_test.788649804
/workspace/coverage/cover_reg_top/44.i2c_intr_test.290085800
/workspace/coverage/cover_reg_top/45.i2c_intr_test.91647227
/workspace/coverage/cover_reg_top/46.i2c_intr_test.3032890077
/workspace/coverage/cover_reg_top/47.i2c_intr_test.2248004029
/workspace/coverage/cover_reg_top/48.i2c_intr_test.883895474
/workspace/coverage/cover_reg_top/49.i2c_intr_test.1528817879
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3717501453
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.2359092456
/workspace/coverage/cover_reg_top/5.i2c_intr_test.1272116758
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.737356276
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.761447860
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3135823634
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2774257763
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.773136655
/workspace/coverage/cover_reg_top/6.i2c_intr_test.3545567356
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2690227915
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2025695999
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.598975490
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1840760288
/workspace/coverage/cover_reg_top/7.i2c_intr_test.1083959650
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2358486756
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.4198695069
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3920382394
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2794181108
/workspace/coverage/cover_reg_top/8.i2c_intr_test.519892491
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.4170601693
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.191441332
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3359473566
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.589272532
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2855098661
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3402276249
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.1253332305
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.345638599

Total test records in report: 163

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.967307318	Jun 22 04:32:00 PM PDT 24	Jun 22 04:32:02 PM PDT 24	52356072 ps
T2	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.3853912427	Jun 22 04:31:44 PM PDT 24	Jun 22 04:31:46 PM PDT 24	50005422 ps
T3	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.389468365	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:03 PM PDT 24	25577258 ps
T8	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2865453844	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:06 PM PDT 24	44120299 ps
T6	/workspace/coverage/cover_reg_top/4.i2c_intr_test.3091677717	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:53 PM PDT 24	23831036 ps
T7	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.773136655	Jun 22 04:31:56 PM PDT 24	Jun 22 04:31:57 PM PDT 24	25702988 ps
T9	/workspace/coverage/cover_reg_top/29.i2c_intr_test.3744238491	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:12 PM PDT 24	41087711 ps
T4	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1257324804	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:54 PM PDT 24	288971161 ps
T5	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1237799039	Jun 22 04:31:46 PM PDT 24	Jun 22 04:31:50 PM PDT 24	1270158553 ps
T14	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.68685489	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:04 PM PDT 24	200171569 ps
T22	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2905654101	Jun 22 04:32:00 PM PDT 24	Jun 22 04:32:02 PM PDT 24	66420076 ps
T10	/workspace/coverage/cover_reg_top/26.i2c_intr_test.1410047334	Jun 22 04:32:11 PM PDT 24	Jun 22 04:32:13 PM PDT 24	27190402 ps
T23	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.2871961405	Jun 22 04:31:46 PM PDT 24	Jun 22 04:31:48 PM PDT 24	48774613 ps
T15	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1850860047	Jun 22 04:32:25 PM PDT 24	Jun 22 04:32:27 PM PDT 24	40973241 ps
T24	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2254361580	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:04 PM PDT 24	41000814 ps
T16	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1330697159	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:04 PM PDT 24	42033827 ps
T12	/workspace/coverage/cover_reg_top/43.i2c_intr_test.788649804	Jun 22 04:32:12 PM PDT 24	Jun 22 04:32:14 PM PDT 24	35522287 ps
T26	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3937135563	Jun 22 04:31:42 PM PDT 24	Jun 22 04:31:46 PM PDT 24	74509465 ps
T29	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3025966426	Jun 22 04:31:41 PM PDT 24	Jun 22 04:31:44 PM PDT 24	189848677 ps
T30	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2690227915	Jun 22 04:31:53 PM PDT 24	Jun 22 04:31:55 PM PDT 24	53827456 ps
T11	/workspace/coverage/cover_reg_top/31.i2c_intr_test.2229221090	Jun 22 04:32:13 PM PDT 24	Jun 22 04:32:14 PM PDT 24	28167838 ps
T40	/workspace/coverage/cover_reg_top/36.i2c_intr_test.2564688230	Jun 22 04:32:13 PM PDT 24	Jun 22 04:32:14 PM PDT 24	125471338 ps
T31	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.737356276	Jun 22 04:31:49 PM PDT 24	Jun 22 04:31:51 PM PDT 24	65720330 ps
T13	/workspace/coverage/cover_reg_top/0.i2c_intr_test.1075512683	Jun 22 04:31:44 PM PDT 24	Jun 22 04:31:45 PM PDT 24	88089762 ps
T25	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3394994711	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:06 PM PDT 24	153438256 ps
T17	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2638580314	Jun 22 04:32:21 PM PDT 24	Jun 22 04:32:23 PM PDT 24	48207682 ps
T18	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2465136009	Jun 22 04:31:54 PM PDT 24	Jun 22 04:31:57 PM PDT 24	301839188 ps
T64	/workspace/coverage/cover_reg_top/32.i2c_intr_test.3364750919	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:12 PM PDT 24	29739107 ps
T32	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3170755602	Jun 22 04:31:44 PM PDT 24	Jun 22 04:31:46 PM PDT 24	78511937 ps
T33	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2999894567	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:54 PM PDT 24	77747496 ps
T34	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3578868909	Jun 22 04:31:42 PM PDT 24	Jun 22 04:31:44 PM PDT 24	23155804 ps
T50	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1439151249	Jun 22 04:31:53 PM PDT 24	Jun 22 04:31:55 PM PDT 24	44276192 ps
T62	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.1213950948	Jun 22 04:32:08 PM PDT 24	Jun 22 04:32:09 PM PDT 24	115322515 ps
T51	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1480864404	Jun 22 04:32:11 PM PDT 24	Jun 22 04:32:13 PM PDT 24	27035055 ps
T45	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1197099789	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:06 PM PDT 24	109328740 ps
T35	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.2359092456	Jun 22 04:32:32 PM PDT 24	Jun 22 04:32:33 PM PDT 24	175683559 ps
T70	/workspace/coverage/cover_reg_top/11.i2c_intr_test.2899925988	Jun 22 04:32:00 PM PDT 24	Jun 22 04:32:01 PM PDT 24	54176866 ps
T36	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2074807788	Jun 22 04:31:48 PM PDT 24	Jun 22 04:31:49 PM PDT 24	21492617 ps
T68	/workspace/coverage/cover_reg_top/8.i2c_intr_test.519892491	Jun 22 04:31:53 PM PDT 24	Jun 22 04:31:54 PM PDT 24	16996414 ps
T19	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.1619907381	Jun 22 04:32:07 PM PDT 24	Jun 22 04:32:10 PM PDT 24	104011597 ps
T46	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3620709740	Jun 22 04:31:44 PM PDT 24	Jun 22 04:31:46 PM PDT 24	657729865 ps
T20	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1319007020	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:03 PM PDT 24	43192037 ps
T72	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.295245454	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:06 PM PDT 24	30463492 ps
T69	/workspace/coverage/cover_reg_top/20.i2c_intr_test.3032698966	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:04 PM PDT 24	118582258 ps
T47	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2653751734	Jun 22 04:31:45 PM PDT 24	Jun 22 04:31:49 PM PDT 24	331585838 ps
T21	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.982503016	Jun 22 04:31:59 PM PDT 24	Jun 22 04:32:01 PM PDT 24	75834952 ps
T65	/workspace/coverage/cover_reg_top/17.i2c_intr_test.189517180	Jun 22 04:31:59 PM PDT 24	Jun 22 04:32:00 PM PDT 24	44216637 ps
T48	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2419792479	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:05 PM PDT 24	103450705 ps
T27	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1029422195	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:07 PM PDT 24	959447809 ps
T54	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2110262946	Jun 22 04:31:40 PM PDT 24	Jun 22 04:31:43 PM PDT 24	50360995 ps
T59	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2452963900	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:06 PM PDT 24	45796067 ps
T28	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3163126495	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:55 PM PDT 24	156012432 ps
T71	/workspace/coverage/cover_reg_top/30.i2c_intr_test.1228286163	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:12 PM PDT 24	44402843 ps
T73	/workspace/coverage/cover_reg_top/45.i2c_intr_test.91647227	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:12 PM PDT 24	62763765 ps
T67	/workspace/coverage/cover_reg_top/46.i2c_intr_test.3032890077	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:11 PM PDT 24	14805818 ps
T74	/workspace/coverage/cover_reg_top/18.i2c_intr_test.900248181	Jun 22 04:32:07 PM PDT 24	Jun 22 04:32:08 PM PDT 24	73921050 ps
T75	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3222213841	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:05 PM PDT 24	109473420 ps
T66	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1256586861	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:11 PM PDT 24	59156476 ps
T76	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3564863405	Jun 22 04:32:08 PM PDT 24	Jun 22 04:32:09 PM PDT 24	152860540 ps
T77	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2774257763	Jun 22 04:31:51 PM PDT 24	Jun 22 04:31:54 PM PDT 24	85239126 ps
T49	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.3688060185	Jun 22 04:32:52 PM PDT 24	Jun 22 04:32:54 PM PDT 24	236950062 ps
T78	/workspace/coverage/cover_reg_top/15.i2c_intr_test.4088010776	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:04 PM PDT 24	30984765 ps
T37	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3311158829	Jun 22 04:31:41 PM PDT 24	Jun 22 04:31:43 PM PDT 24	21131151 ps
T79	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3891046214	Jun 22 04:31:59 PM PDT 24	Jun 22 04:32:00 PM PDT 24	49099236 ps
T80	/workspace/coverage/cover_reg_top/23.i2c_intr_test.617326154	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:05 PM PDT 24	55644297 ps
T81	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3260312847	Jun 22 04:32:07 PM PDT 24	Jun 22 04:32:08 PM PDT 24	63972286 ps
T82	/workspace/coverage/cover_reg_top/47.i2c_intr_test.2248004029	Jun 22 04:32:11 PM PDT 24	Jun 22 04:32:13 PM PDT 24	38386796 ps
T83	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.4272584288	Jun 22 04:31:42 PM PDT 24	Jun 22 04:31:44 PM PDT 24	50151969 ps
T84	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.685937992	Jun 22 04:31:45 PM PDT 24	Jun 22 04:31:48 PM PDT 24	123601972 ps
T85	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1564981512	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:07 PM PDT 24	39858194 ps
T86	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1885602581	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:06 PM PDT 24	170855932 ps
T87	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.158729871	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:04 PM PDT 24	17143097 ps
T88	/workspace/coverage/cover_reg_top/14.i2c_intr_test.1412684732	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:04 PM PDT 24	39587502 ps
T89	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2358486756	Jun 22 04:31:50 PM PDT 24	Jun 22 04:31:53 PM PDT 24	136771844 ps
T90	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.191441332	Jun 22 04:31:50 PM PDT 24	Jun 22 04:31:53 PM PDT 24	342249782 ps
T91	/workspace/coverage/cover_reg_top/44.i2c_intr_test.290085800	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:11 PM PDT 24	21919355 ps
T92	/workspace/coverage/cover_reg_top/22.i2c_intr_test.114288490	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:06 PM PDT 24	16011939 ps
T93	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.919245559	Jun 22 04:31:48 PM PDT 24	Jun 22 04:31:50 PM PDT 24	192439405 ps
T94	/workspace/coverage/cover_reg_top/37.i2c_intr_test.2474765444	Jun 22 04:32:11 PM PDT 24	Jun 22 04:32:13 PM PDT 24	20345923 ps
T53	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4147923666	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:07 PM PDT 24	136427115 ps
T95	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3027066995	Jun 22 04:31:46 PM PDT 24	Jun 22 04:31:49 PM PDT 24	35030237 ps
T96	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3294670534	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:06 PM PDT 24	266761432 ps
T97	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.698090619	Jun 22 04:31:43 PM PDT 24	Jun 22 04:31:45 PM PDT 24	27231084 ps
T98	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1918186366	Jun 22 04:32:13 PM PDT 24	Jun 22 04:32:15 PM PDT 24	15814456 ps
T38	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2434678966	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:05 PM PDT 24	50569443 ps
T99	/workspace/coverage/cover_reg_top/24.i2c_intr_test.405218749	Jun 22 04:32:11 PM PDT 24	Jun 22 04:32:13 PM PDT 24	19716526 ps
T100	/workspace/coverage/cover_reg_top/9.i2c_intr_test.2855098661	Jun 22 04:31:55 PM PDT 24	Jun 22 04:31:56 PM PDT 24	19741764 ps
T55	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3135823634	Jun 22 04:31:55 PM PDT 24	Jun 22 04:31:57 PM PDT 24	166428568 ps
T101	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3402276249	Jun 22 04:31:50 PM PDT 24	Jun 22 04:31:52 PM PDT 24	91543244 ps
T102	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3615045547	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:11 PM PDT 24	35828952 ps
T103	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2303594200	Jun 22 04:32:00 PM PDT 24	Jun 22 04:32:02 PM PDT 24	403737488 ps
T104	/workspace/coverage/cover_reg_top/19.i2c_intr_test.2243392810	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:02 PM PDT 24	18575789 ps
T105	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2794181108	Jun 22 04:31:53 PM PDT 24	Jun 22 04:31:55 PM PDT 24	50774986 ps
T106	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.536206186	Jun 22 04:31:51 PM PDT 24	Jun 22 04:31:55 PM PDT 24	903308937 ps
T107	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3359473566	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:54 PM PDT 24	192550376 ps
T108	/workspace/coverage/cover_reg_top/35.i2c_intr_test.1195980829	Jun 22 04:32:12 PM PDT 24	Jun 22 04:32:14 PM PDT 24	31024285 ps
T109	/workspace/coverage/cover_reg_top/3.i2c_intr_test.415259888	Jun 22 04:31:50 PM PDT 24	Jun 22 04:31:52 PM PDT 24	29419611 ps
T60	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1349506003	Jun 22 04:32:05 PM PDT 24	Jun 22 04:32:07 PM PDT 24	58241669 ps
T57	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.250989818	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:03 PM PDT 24	502890673 ps
T110	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2399420914	Jun 22 04:31:42 PM PDT 24	Jun 22 04:31:44 PM PDT 24	124363212 ps
T111	/workspace/coverage/cover_reg_top/42.i2c_intr_test.996763925	Jun 22 04:32:12 PM PDT 24	Jun 22 04:32:14 PM PDT 24	53040373 ps
T112	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2832269277	Jun 22 04:31:44 PM PDT 24	Jun 22 04:31:47 PM PDT 24	128774024 ps
T56	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.728867758	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:07 PM PDT 24	87970437 ps
T113	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3481516606	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:04 PM PDT 24	31380808 ps
T114	/workspace/coverage/cover_reg_top/5.i2c_intr_test.1272116758	Jun 22 04:31:51 PM PDT 24	Jun 22 04:31:53 PM PDT 24	61020637 ps
T115	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2098228367	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:04 PM PDT 24	43108783 ps
T116	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3729567951	Jun 22 04:32:05 PM PDT 24	Jun 22 04:32:07 PM PDT 24	64123299 ps
T117	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1840760288	Jun 22 04:31:51 PM PDT 24	Jun 22 04:31:53 PM PDT 24	57477260 ps
T118	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.723617287	Jun 22 04:31:48 PM PDT 24	Jun 22 04:31:50 PM PDT 24	65894177 ps
T119	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1986473256	Jun 22 04:31:53 PM PDT 24	Jun 22 04:31:55 PM PDT 24	29176677 ps
T61	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3108951328	Jun 22 04:31:53 PM PDT 24	Jun 22 04:31:55 PM PDT 24	199656250 ps
T120	/workspace/coverage/cover_reg_top/16.i2c_intr_test.1182337337	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:03 PM PDT 24	46878988 ps
T121	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3852321890	Jun 22 04:31:46 PM PDT 24	Jun 22 04:31:51 PM PDT 24	662121835 ps
T122	/workspace/coverage/cover_reg_top/1.i2c_intr_test.1557159395	Jun 22 04:31:41 PM PDT 24	Jun 22 04:31:43 PM PDT 24	26367679 ps
T123	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2025695999	Jun 22 04:31:50 PM PDT 24	Jun 22 04:31:52 PM PDT 24	325916376 ps
T124	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.1030849281	Jun 22 04:31:49 PM PDT 24	Jun 22 04:31:51 PM PDT 24	17788172 ps
T125	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.4198695069	Jun 22 04:31:56 PM PDT 24	Jun 22 04:31:58 PM PDT 24	45615065 ps
T126	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4065803435	Jun 22 04:31:44 PM PDT 24	Jun 22 04:31:48 PM PDT 24	887944992 ps
T127	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3919110494	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:04 PM PDT 24	223832250 ps
T128	/workspace/coverage/cover_reg_top/48.i2c_intr_test.883895474	Jun 22 04:32:12 PM PDT 24	Jun 22 04:32:14 PM PDT 24	42487952 ps
T129	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.222234853	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:54 PM PDT 24	142534830 ps
T130	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3920382394	Jun 22 04:31:55 PM PDT 24	Jun 22 04:31:57 PM PDT 24	23985598 ps
T131	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.3717247160	Jun 22 04:32:00 PM PDT 24	Jun 22 04:32:02 PM PDT 24	367396174 ps
T132	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3956797043	Jun 22 04:31:43 PM PDT 24	Jun 22 04:31:46 PM PDT 24	517927691 ps
T133	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.4219970463	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:05 PM PDT 24	129095972 ps
T134	/workspace/coverage/cover_reg_top/27.i2c_intr_test.4043086185	Jun 22 04:32:11 PM PDT 24	Jun 22 04:32:13 PM PDT 24	31982101 ps
T135	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1868108333	Jun 22 04:31:40 PM PDT 24	Jun 22 04:31:42 PM PDT 24	23381192 ps
T136	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.404247857	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:55 PM PDT 24	166582589 ps
T137	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1978064125	Jun 22 04:31:43 PM PDT 24	Jun 22 04:31:44 PM PDT 24	42202624 ps
T138	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.345638599	Jun 22 04:31:54 PM PDT 24	Jun 22 04:31:58 PM PDT 24	271471152 ps
T139	/workspace/coverage/cover_reg_top/2.i2c_intr_test.3851764434	Jun 22 04:31:45 PM PDT 24	Jun 22 04:31:48 PM PDT 24	22104682 ps
T140	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2754790907	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:05 PM PDT 24	1214390339 ps
T63	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3266403034	Jun 22 04:31:46 PM PDT 24	Jun 22 04:31:48 PM PDT 24	59529680 ps
T39	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1078981636	Jun 22 04:31:49 PM PDT 24	Jun 22 04:31:51 PM PDT 24	102161743 ps
T141	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.761447860	Jun 22 04:31:49 PM PDT 24	Jun 22 04:31:53 PM PDT 24	88348707 ps
T142	/workspace/coverage/cover_reg_top/39.i2c_intr_test.3395892514	Jun 22 04:32:10 PM PDT 24	Jun 22 04:32:11 PM PDT 24	32271380 ps
T143	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2515750758	Jun 22 04:32:00 PM PDT 24	Jun 22 04:32:02 PM PDT 24	36572064 ps
T144	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.1412236105	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:04 PM PDT 24	35636011 ps
T41	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2352535573	Jun 22 04:31:44 PM PDT 24	Jun 22 04:31:46 PM PDT 24	52397120 ps
T145	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.4170601693	Jun 22 04:31:55 PM PDT 24	Jun 22 04:31:58 PM PDT 24	322127327 ps
T146	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1322963349	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:06 PM PDT 24	117889988 ps
T147	/workspace/coverage/cover_reg_top/40.i2c_intr_test.469482711	Jun 22 04:32:07 PM PDT 24	Jun 22 04:32:09 PM PDT 24	41529639 ps
T58	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3300011655	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:05 PM PDT 24	143786811 ps
T148	/workspace/coverage/cover_reg_top/6.i2c_intr_test.3545567356	Jun 22 04:31:54 PM PDT 24	Jun 22 04:31:56 PM PDT 24	52397861 ps
T42	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1955851913	Jun 22 04:31:54 PM PDT 24	Jun 22 04:31:57 PM PDT 24	47204293 ps
T149	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.598975490	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:54 PM PDT 24	39344910 ps
T150	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.454036415	Jun 22 04:31:46 PM PDT 24	Jun 22 04:31:49 PM PDT 24	61787235 ps
T43	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.877585648	Jun 22 04:31:54 PM PDT 24	Jun 22 04:31:56 PM PDT 24	49096391 ps
T151	/workspace/coverage/cover_reg_top/34.i2c_intr_test.50034498	Jun 22 04:32:09 PM PDT 24	Jun 22 04:32:10 PM PDT 24	158597907 ps
T44	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1577820121	Jun 22 04:32:00 PM PDT 24	Jun 22 04:32:01 PM PDT 24	16241790 ps
T152	/workspace/coverage/cover_reg_top/38.i2c_intr_test.3894436059	Jun 22 04:32:11 PM PDT 24	Jun 22 04:32:13 PM PDT 24	37307466 ps
T153	/workspace/coverage/cover_reg_top/13.i2c_intr_test.197035454	Jun 22 04:32:03 PM PDT 24	Jun 22 04:32:06 PM PDT 24	101327735 ps
T154	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.898419409	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:05 PM PDT 24	107759619 ps
T155	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.414096605	Jun 22 04:32:02 PM PDT 24	Jun 22 04:32:05 PM PDT 24	99996480 ps
T156	/workspace/coverage/cover_reg_top/49.i2c_intr_test.1528817879	Jun 22 04:32:07 PM PDT 24	Jun 22 04:32:09 PM PDT 24	48832659 ps
T157	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.1253332305	Jun 22 04:31:55 PM PDT 24	Jun 22 04:31:58 PM PDT 24	209255722 ps
T158	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.3140077641	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:54 PM PDT 24	75428630 ps
T52	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2170628888	Jun 22 04:31:54 PM PDT 24	Jun 22 04:31:56 PM PDT 24	27617138 ps
T159	/workspace/coverage/cover_reg_top/12.i2c_intr_test.2450291055	Jun 22 04:32:04 PM PDT 24	Jun 22 04:32:06 PM PDT 24	20702303 ps
T160	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3717501453	Jun 22 04:31:51 PM PDT 24	Jun 22 04:31:53 PM PDT 24	38168610 ps
T161	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1579848148	Jun 22 04:32:01 PM PDT 24	Jun 22 04:32:03 PM PDT 24	39058984 ps
T162	/workspace/coverage/cover_reg_top/7.i2c_intr_test.1083959650	Jun 22 04:31:53 PM PDT 24	Jun 22 04:31:55 PM PDT 24	59904942 ps
T163	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.589272532	Jun 22 04:31:52 PM PDT 24	Jun 22 04:31:54 PM PDT 24	87225143 ps

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1237799039
Short name	T5
Test name
Test status
Simulation time	1270158553 ps
CPU time	2.5 seconds
Started	Jun 22 04:31:46 PM PDT 24
Finished	Jun 22 04:31:50 PM PDT 24
Peak memory	204220 kb
Host	smart-ea9c86e6-0ab6-4cd2-a80d-baf7da9b7af5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237799039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1237799039
Directory	/workspace/0.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/31.i2c_intr_test.2229221090
Short name	T11
Test name
Test status
Simulation time	28167838 ps
CPU time	0.66 seconds
Started	Jun 22 04:32:13 PM PDT 24
Finished	Jun 22 04:32:14 PM PDT 24
Peak memory	204008 kb
Host	smart-e41f4aba-54e2-482f-a0cb-954c394d5829
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229221090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2229221090
Directory	/workspace/31.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2465136009
Short name	T18
Test name
Test status
Simulation time	301839188 ps
CPU time	2.26 seconds
Started	Jun 22 04:31:54 PM PDT 24
Finished	Jun 22 04:31:57 PM PDT 24
Peak memory	204340 kb
Host	smart-4ffed05a-b5fb-4a1e-bb97-8afbd8da9f38
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465136009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2465136009
Directory	/workspace/6.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.2871961405
Short name	T23
Test name
Test status
Simulation time	48774613 ps
CPU time	0.78 seconds
Started	Jun 22 04:31:46 PM PDT 24
Finished	Jun 22 04:31:48 PM PDT 24
Peak memory	204044 kb
Host	smart-a528b82e-d27d-4484-bd68-5784e1c5c758
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871961405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2871961405
Directory	/workspace/1.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1480864404
Short name	T51
Test name
Test status
Simulation time	27035055 ps
CPU time	0.68 seconds
Started	Jun 22 04:32:11 PM PDT 24
Finished	Jun 22 04:32:13 PM PDT 24
Peak memory	204008 kb
Host	smart-0c1dd257-0369-4c46-b59b-c143dd48b440
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480864404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1480864404
Directory	/workspace/33.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.i2c_intr_test.1410047334
Short name	T10
Test name
Test status
Simulation time	27190402 ps
CPU time	0.68 seconds
Started	Jun 22 04:32:11 PM PDT 24
Finished	Jun 22 04:32:13 PM PDT 24
Peak memory	204008 kb
Host	smart-27375bf8-28fe-447f-ba12-34c178ce3c64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410047334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1410047334
Directory	/workspace/26.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1330697159
Short name	T16
Test name
Test status
Simulation time	42033827 ps
CPU time	1.02 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	204096 kb
Host	smart-c52c16ce-0ef6-4db6-b274-2881a90790bd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330697159 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1330697159
Directory	/workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/30.i2c_intr_test.1228286163
Short name	T71
Test name
Test status
Simulation time	44402843 ps
CPU time	0.67 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:12 PM PDT 24
Peak memory	204024 kb
Host	smart-e2b97594-05f5-46d5-a7ce-556a7aadca24
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228286163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1228286163
Directory	/workspace/30.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3108951328
Short name	T61
Test name
Test status
Simulation time	199656250 ps
CPU time	1.15 seconds
Started	Jun 22 04:31:53 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204192 kb
Host	smart-ed193057-cf2e-4b8a-9e47-841c82d0111c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108951328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.3108951328
Directory	/workspace/8.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1256586861
Short name	T66
Test name
Test status
Simulation time	59156476 ps
CPU time	0.67 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:11 PM PDT 24
Peak memory	204008 kb
Host	smart-c78a47a7-9ab1-479c-b75e-4e3a580e7ba5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256586861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1256586861
Directory	/workspace/25.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1029422195
Short name	T27
Test name
Test status
Simulation time	959447809 ps
CPU time	2.6 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:07 PM PDT 24
Peak memory	204300 kb
Host	smart-d4c5953b-cd87-4a6d-99ac-88cc21cba7f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029422195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1029422195
Directory	/workspace/14.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.1619907381
Short name	T19
Test name
Test status
Simulation time	104011597 ps
CPU time	2.18 seconds
Started	Jun 22 04:32:07 PM PDT 24
Finished	Jun 22 04:32:10 PM PDT 24
Peak memory	204340 kb
Host	smart-87cabf19-9dd4-43d1-aa07-8da2c75f8b99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619907381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1619907381
Directory	/workspace/17.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2170628888
Short name	T52
Test name
Test status
Simulation time	27617138 ps
CPU time	1.12 seconds
Started	Jun 22 04:31:54 PM PDT 24
Finished	Jun 22 04:31:56 PM PDT 24
Peak memory	204224 kb
Host	smart-a6469116-a8f3-4437-96a9-957a5797dbfe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170628888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.2170628888
Directory	/workspace/4.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3311158829
Short name	T37
Test name
Test status
Simulation time	21131151 ps
CPU time	0.76 seconds
Started	Jun 22 04:31:41 PM PDT 24
Finished	Jun 22 04:31:43 PM PDT 24
Peak memory	204168 kb
Host	smart-c80c2c0a-58bb-4840-9c0e-d5cb3c8a2115
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311158829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3311158829
Directory	/workspace/2.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2110262946
Short name	T54
Test name
Test status
Simulation time	50360995 ps
CPU time	1.44 seconds
Started	Jun 22 04:31:40 PM PDT 24
Finished	Jun 22 04:31:43 PM PDT 24
Peak memory	204216 kb
Host	smart-6ea00aea-a5b8-4ad3-ae87-67fae0229374
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110262946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2110262946
Directory	/workspace/1.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3266403034
Short name	T63
Test name
Test status
Simulation time	59529680 ps
CPU time	0.71 seconds
Started	Jun 22 04:31:46 PM PDT 24
Finished	Jun 22 04:31:48 PM PDT 24
Peak memory	204000 kb
Host	smart-55a6185f-decb-4adb-9d51-1fd770bab8ac
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266403034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3266403034
Directory	/workspace/1.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4147923666
Short name	T53
Test name
Test status
Simulation time	136427115 ps
CPU time	2.51 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:07 PM PDT 24
Peak memory	204272 kb
Host	smart-9a11a985-8fe8-4779-8f8d-bbf72c7b031d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147923666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.4147923666
Directory	/workspace/15.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2352535573
Short name	T41
Test name
Test status
Simulation time	52397120 ps
CPU time	1.37 seconds
Started	Jun 22 04:31:44 PM PDT 24
Finished	Jun 22 04:31:46 PM PDT 24
Peak memory	204328 kb
Host	smart-057b1ec1-0e43-46c8-9908-3149d570b6db
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352535573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2352535573
Directory	/workspace/0.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4065803435
Short name	T126
Test name
Test status
Simulation time	887944992 ps
CPU time	3.13 seconds
Started	Jun 22 04:31:44 PM PDT 24
Finished	Jun 22 04:31:48 PM PDT 24
Peak memory	204268 kb
Host	smart-d706157c-bade-4685-937b-584fdf16f808
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065803435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.4065803435
Directory	/workspace/0.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3578868909
Short name	T34
Test name
Test status
Simulation time	23155804 ps
CPU time	0.72 seconds
Started	Jun 22 04:31:42 PM PDT 24
Finished	Jun 22 04:31:44 PM PDT 24
Peak memory	203932 kb
Host	smart-0f5e437d-bf66-46d2-a05d-7d9509b6b36e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578868909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3578868909
Directory	/workspace/0.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.723617287
Short name	T118
Test name
Test status
Simulation time	65894177 ps
CPU time	0.91 seconds
Started	Jun 22 04:31:48 PM PDT 24
Finished	Jun 22 04:31:50 PM PDT 24
Peak memory	204092 kb
Host	smart-b455c00e-0668-407e-b422-c95590752b1f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723617287 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.723617287
Directory	/workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1868108333
Short name	T135
Test name
Test status
Simulation time	23381192 ps
CPU time	0.77 seconds
Started	Jun 22 04:31:40 PM PDT 24
Finished	Jun 22 04:31:42 PM PDT 24
Peak memory	203984 kb
Host	smart-b6ab60f1-05b7-4521-b93c-0afeda2866f5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868108333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1868108333
Directory	/workspace/0.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_intr_test.1075512683
Short name	T13
Test name
Test status
Simulation time	88089762 ps
CPU time	0.69 seconds
Started	Jun 22 04:31:44 PM PDT 24
Finished	Jun 22 04:31:45 PM PDT 24
Peak memory	204084 kb
Host	smart-0a98ce28-0f14-441f-a443-0d1469f36fb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075512683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1075512683
Directory	/workspace/0.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3956797043
Short name	T132
Test name
Test status
Simulation time	517927691 ps
CPU time	0.94 seconds
Started	Jun 22 04:31:43 PM PDT 24
Finished	Jun 22 04:31:46 PM PDT 24
Peak memory	204036 kb
Host	smart-6b391c5c-f0d2-4c64-a9cf-2a46b0bfc840
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956797043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.3956797043
Directory	/workspace/0.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.919245559
Short name	T93
Test name
Test status
Simulation time	192439405 ps
CPU time	1.45 seconds
Started	Jun 22 04:31:48 PM PDT 24
Finished	Jun 22 04:31:50 PM PDT 24
Peak memory	204324 kb
Host	smart-305308bf-c952-4612-9ef6-85e370774181
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919245559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.919245559
Directory	/workspace/0.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1078981636
Short name	T39
Test name
Test status
Simulation time	102161743 ps
CPU time	1.91 seconds
Started	Jun 22 04:31:49 PM PDT 24
Finished	Jun 22 04:31:51 PM PDT 24
Peak memory	204268 kb
Host	smart-10341389-90df-4800-8eca-577e40e32962
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078981636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1078981636
Directory	/workspace/1.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3852321890
Short name	T121
Test name
Test status
Simulation time	662121835 ps
CPU time	3.43 seconds
Started	Jun 22 04:31:46 PM PDT 24
Finished	Jun 22 04:31:51 PM PDT 24
Peak memory	204172 kb
Host	smart-472c60ad-4903-4605-8757-b84e8f17f5e2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852321890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3852321890
Directory	/workspace/1.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.698090619
Short name	T97
Test name
Test status
Simulation time	27231084 ps
CPU time	0.84 seconds
Started	Jun 22 04:31:43 PM PDT 24
Finished	Jun 22 04:31:45 PM PDT 24
Peak memory	204096 kb
Host	smart-9dbe082d-9fac-4608-a76a-4334c60d0854
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698090619 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.698090619
Directory	/workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_intr_test.1557159395
Short name	T122
Test name
Test status
Simulation time	26367679 ps
CPU time	0.64 seconds
Started	Jun 22 04:31:41 PM PDT 24
Finished	Jun 22 04:31:43 PM PDT 24
Peak memory	204000 kb
Host	smart-d39668a9-e0f6-4a3d-b006-a74848724e42
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557159395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1557159395
Directory	/workspace/1.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.685937992
Short name	T84
Test name
Test status
Simulation time	123601972 ps
CPU time	1.11 seconds
Started	Jun 22 04:31:45 PM PDT 24
Finished	Jun 22 04:31:48 PM PDT 24
Peak memory	204304 kb
Host	smart-1cca2540-49a6-4c85-b0bb-83fde34cdef8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685937992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out standing.685937992
Directory	/workspace/1.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.4272584288
Short name	T83
Test name
Test status
Simulation time	50151969 ps
CPU time	1.18 seconds
Started	Jun 22 04:31:42 PM PDT 24
Finished	Jun 22 04:31:44 PM PDT 24
Peak memory	204296 kb
Host	smart-a079ff75-4d30-4f1f-b45a-ecfefcf8c8a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272584288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.4272584288
Directory	/workspace/1.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2515750758
Short name	T143
Test name
Test status
Simulation time	36572064 ps
CPU time	1.03 seconds
Started	Jun 22 04:32:00 PM PDT 24
Finished	Jun 22 04:32:02 PM PDT 24
Peak memory	204096 kb
Host	smart-091f54c7-2f6f-4d56-864d-49dc0e6f450e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515750758 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2515750758
Directory	/workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.877585648
Short name	T43
Test name
Test status
Simulation time	49096391 ps
CPU time	0.73 seconds
Started	Jun 22 04:31:54 PM PDT 24
Finished	Jun 22 04:31:56 PM PDT 24
Peak memory	204020 kb
Host	smart-13a8697c-5164-4410-884a-ef6d8106b667
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877585648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.877585648
Directory	/workspace/10.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1439151249
Short name	T50
Test name
Test status
Simulation time	44276192 ps
CPU time	0.71 seconds
Started	Jun 22 04:31:53 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204020 kb
Host	smart-e1795a82-55da-474e-92fc-1deb90079bd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439151249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1439151249
Directory	/workspace/10.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2905654101
Short name	T22
Test name
Test status
Simulation time	66420076 ps
CPU time	0.93 seconds
Started	Jun 22 04:32:00 PM PDT 24
Finished	Jun 22 04:32:02 PM PDT 24
Peak memory	204100 kb
Host	smart-1d289755-bb9e-4cad-898b-4bca4468ffed
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905654101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.2905654101
Directory	/workspace/10.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.3688060185
Short name	T49
Test name
Test status
Simulation time	236950062 ps
CPU time	1.5 seconds
Started	Jun 22 04:32:52 PM PDT 24
Finished	Jun 22 04:32:54 PM PDT 24
Peak memory	204256 kb
Host	smart-99cb82bc-b955-44b7-9a3b-17a0c18b1ca6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688060185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3688060185
Directory	/workspace/10.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1257324804
Short name	T4
Test name
Test status
Simulation time	288971161 ps
CPU time	1.6 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204276 kb
Host	smart-c699322e-692a-48cd-b4a2-0f1d7d8f4942
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257324804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1257324804
Directory	/workspace/10.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3222213841
Short name	T75
Test name
Test status
Simulation time	109473420 ps
CPU time	1.02 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	204168 kb
Host	smart-6e10da2f-9c54-493d-8126-eba7a8f4d84c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222213841 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3222213841
Directory	/workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.158729871
Short name	T87
Test name
Test status
Simulation time	17143097 ps
CPU time	0.71 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	204036 kb
Host	smart-8059f26e-f46e-4781-a007-200b3fd054d6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158729871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.158729871
Directory	/workspace/11.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_intr_test.2899925988
Short name	T70
Test name
Test status
Simulation time	54176866 ps
CPU time	0.65 seconds
Started	Jun 22 04:32:00 PM PDT 24
Finished	Jun 22 04:32:01 PM PDT 24
Peak memory	204004 kb
Host	smart-d9c4e792-2134-4c8c-9818-4f218f559456
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899925988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2899925988
Directory	/workspace/11.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1349506003
Short name	T60
Test name
Test status
Simulation time	58241669 ps
CPU time	1.16 seconds
Started	Jun 22 04:32:05 PM PDT 24
Finished	Jun 22 04:32:07 PM PDT 24
Peak memory	204228 kb
Host	smart-2c90b174-0736-40e2-965e-5614e9e39ef5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349506003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.1349506003
Directory	/workspace/11.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1322963349
Short name	T146
Test name
Test status
Simulation time	117889988 ps
CPU time	2.18 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204340 kb
Host	smart-e5504f4d-be70-4ad9-a6f1-e2bd5ca924d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322963349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1322963349
Directory	/workspace/11.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.250989818
Short name	T57
Test name
Test status
Simulation time	502890673 ps
CPU time	1.46 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:03 PM PDT 24
Peak memory	204232 kb
Host	smart-e663f880-c176-451a-b694-e0ba55117042
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250989818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.250989818
Directory	/workspace/11.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3729567951
Short name	T116
Test name
Test status
Simulation time	64123299 ps
CPU time	0.97 seconds
Started	Jun 22 04:32:05 PM PDT 24
Finished	Jun 22 04:32:07 PM PDT 24
Peak memory	204064 kb
Host	smart-0d6b4933-d8ee-4731-a06f-553109211ef9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729567951 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3729567951
Directory	/workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.1412236105
Short name	T144
Test name
Test status
Simulation time	35636011 ps
CPU time	0.7 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	203952 kb
Host	smart-91360d38-29cc-47a1-bfae-1fd3066eb168
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412236105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1412236105
Directory	/workspace/12.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_intr_test.2450291055
Short name	T159
Test name
Test status
Simulation time	20702303 ps
CPU time	0.69 seconds
Started	Jun 22 04:32:04 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204000 kb
Host	smart-ff706e42-250f-4067-bc29-256f24193ce0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450291055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2450291055
Directory	/workspace/12.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1197099789
Short name	T45
Test name
Test status
Simulation time	109328740 ps
CPU time	0.93 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204004 kb
Host	smart-a6c6f0c5-656e-4f44-bde2-525e6dc9a836
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197099789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.1197099789
Directory	/workspace/12.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.68685489
Short name	T14
Test name
Test status
Simulation time	200171569 ps
CPU time	1.41 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	204300 kb
Host	smart-b923aa0f-9d6b-418e-81c6-f324706d3ef3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68685489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.68685489
Directory	/workspace/12.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3300011655
Short name	T58
Test name
Test status
Simulation time	143786811 ps
CPU time	2.53 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	204280 kb
Host	smart-5cc2db89-0b50-4c70-b9aa-210e8f708304
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300011655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3300011655
Directory	/workspace/12.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.414096605
Short name	T155
Test name
Test status
Simulation time	99996480 ps
CPU time	1.25 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	204280 kb
Host	smart-43c3a7da-1eab-4810-b7db-86f1c352a9e6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414096605 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.414096605
Directory	/workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2254361580
Short name	T24
Test name
Test status
Simulation time	41000814 ps
CPU time	0.7 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	203984 kb
Host	smart-c28b922d-463a-4c65-83dc-ca477317592e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254361580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2254361580
Directory	/workspace/13.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_intr_test.197035454
Short name	T153
Test name
Test status
Simulation time	101327735 ps
CPU time	0.69 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204000 kb
Host	smart-40f40247-7f06-408d-bdf5-bb63449cd142
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197035454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.197035454
Directory	/workspace/13.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2452963900
Short name	T59
Test name
Test status
Simulation time	45796067 ps
CPU time	1.33 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204380 kb
Host	smart-a429ba02-4e87-4bc5-9ebc-b99a651c5969
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452963900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.2452963900
Directory	/workspace/13.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.3717247160
Short name	T131
Test name
Test status
Simulation time	367396174 ps
CPU time	1.7 seconds
Started	Jun 22 04:32:00 PM PDT 24
Finished	Jun 22 04:32:02 PM PDT 24
Peak memory	204264 kb
Host	smart-6682d157-6c75-401f-b0a5-fd9b7976f6f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717247160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3717247160
Directory	/workspace/13.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.982503016
Short name	T21
Test name
Test status
Simulation time	75834952 ps
CPU time	1.54 seconds
Started	Jun 22 04:31:59 PM PDT 24
Finished	Jun 22 04:32:01 PM PDT 24
Peak memory	204300 kb
Host	smart-2d017269-f601-446d-9738-20116ef170c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982503016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.982503016
Directory	/workspace/13.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1850860047
Short name	T15
Test name
Test status
Simulation time	40973241 ps
CPU time	1.05 seconds
Started	Jun 22 04:32:25 PM PDT 24
Finished	Jun 22 04:32:27 PM PDT 24
Peak memory	219964 kb
Host	smart-723bffce-b0e2-4e03-887d-8fb441de1d1b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850860047 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1850860047
Directory	/workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.389468365
Short name	T3
Test name
Test status
Simulation time	25577258 ps
CPU time	0.68 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:03 PM PDT 24
Peak memory	204004 kb
Host	smart-2057431c-40e9-4839-9387-b4bf55b2a259
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389468365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.389468365
Directory	/workspace/14.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_intr_test.1412684732
Short name	T88
Test name
Test status
Simulation time	39587502 ps
CPU time	0.69 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	203972 kb
Host	smart-6c9ceb79-4393-4f9e-af5d-9ffcba5d0379
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412684732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1412684732
Directory	/workspace/14.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.295245454
Short name	T72
Test name
Test status
Simulation time	30463492 ps
CPU time	1.36 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204376 kb
Host	smart-f88f0f13-e162-47df-84be-3bee3bf7f455
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295245454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou tstanding.295245454
Directory	/workspace/14.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2303594200
Short name	T103
Test name
Test status
Simulation time	403737488 ps
CPU time	2.04 seconds
Started	Jun 22 04:32:00 PM PDT 24
Finished	Jun 22 04:32:02 PM PDT 24
Peak memory	204448 kb
Host	smart-6a617924-6ba0-4a71-ba55-3e7685f1622f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303594200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2303594200
Directory	/workspace/14.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3919110494
Short name	T127
Test name
Test status
Simulation time	223832250 ps
CPU time	1 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	204096 kb
Host	smart-564cc549-645f-4061-bf7f-dd9c9255e18b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919110494 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3919110494
Directory	/workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1577820121
Short name	T44
Test name
Test status
Simulation time	16241790 ps
CPU time	0.69 seconds
Started	Jun 22 04:32:00 PM PDT 24
Finished	Jun 22 04:32:01 PM PDT 24
Peak memory	204004 kb
Host	smart-4ca51623-13a5-4494-a485-86398aa804d1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577820121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1577820121
Directory	/workspace/15.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_intr_test.4088010776
Short name	T78
Test name
Test status
Simulation time	30984765 ps
CPU time	0.7 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	204004 kb
Host	smart-9028c3f5-a8ba-4bc8-b054-737f4eab1f02
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088010776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.4088010776
Directory	/workspace/15.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3294670534
Short name	T96
Test name
Test status
Simulation time	266761432 ps
CPU time	0.99 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204004 kb
Host	smart-2004a374-0191-44d2-b0ca-27b6cf0b0d61
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294670534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.3294670534
Directory	/workspace/15.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3564863405
Short name	T76
Test name
Test status
Simulation time	152860540 ps
CPU time	1.21 seconds
Started	Jun 22 04:32:08 PM PDT 24
Finished	Jun 22 04:32:09 PM PDT 24
Peak memory	204360 kb
Host	smart-73c42dbb-b65c-4ef4-a6f0-6c4b5da8610d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564863405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3564863405
Directory	/workspace/15.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1319007020
Short name	T20
Test name
Test status
Simulation time	43192037 ps
CPU time	0.93 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:03 PM PDT 24
Peak memory	204096 kb
Host	smart-8e577fa3-f555-4354-a341-4be48fff22b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319007020 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1319007020
Directory	/workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2434678966
Short name	T38
Test name
Test status
Simulation time	50569443 ps
CPU time	0.73 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	204036 kb
Host	smart-57cc6ce9-240b-4a5c-9c67-861aa542020e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434678966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2434678966
Directory	/workspace/16.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_intr_test.1182337337
Short name	T120
Test name
Test status
Simulation time	46878988 ps
CPU time	0.74 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:03 PM PDT 24
Peak memory	203976 kb
Host	smart-d03362d8-9829-40e6-a9a7-15cd3845e93d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182337337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1182337337
Directory	/workspace/16.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1579848148
Short name	T161
Test name
Test status
Simulation time	39058984 ps
CPU time	0.85 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:03 PM PDT 24
Peak memory	204004 kb
Host	smart-63713c99-2324-444d-bb25-ff6499ca996c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579848148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.1579848148
Directory	/workspace/16.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2638580314
Short name	T17
Test name
Test status
Simulation time	48207682 ps
CPU time	1.26 seconds
Started	Jun 22 04:32:21 PM PDT 24
Finished	Jun 22 04:32:23 PM PDT 24
Peak memory	204280 kb
Host	smart-cf4c6c56-3e43-45a0-8dba-9915cc04094b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638580314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2638580314
Directory	/workspace/16.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2419792479
Short name	T48
Test name
Test status
Simulation time	103450705 ps
CPU time	1.61 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	204232 kb
Host	smart-e8010d02-64e5-475c-a064-e0f949833ed6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419792479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2419792479
Directory	/workspace/16.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3481516606
Short name	T113
Test name
Test status
Simulation time	31380808 ps
CPU time	0.86 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	204064 kb
Host	smart-a333e6b9-3b33-4efd-a479-5ef8518573cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481516606 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3481516606
Directory	/workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2865453844
Short name	T8
Test name
Test status
Simulation time	44120299 ps
CPU time	0.75 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204052 kb
Host	smart-bc1a0cc5-5866-40d1-b2b9-9becf5125095
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865453844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2865453844
Directory	/workspace/17.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_intr_test.189517180
Short name	T65
Test name
Test status
Simulation time	44216637 ps
CPU time	0.68 seconds
Started	Jun 22 04:31:59 PM PDT 24
Finished	Jun 22 04:32:00 PM PDT 24
Peak memory	204008 kb
Host	smart-ad6e521e-04da-4cce-a72e-18702c22dd92
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189517180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.189517180
Directory	/workspace/17.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3260312847
Short name	T81
Test name
Test status
Simulation time	63972286 ps
CPU time	0.87 seconds
Started	Jun 22 04:32:07 PM PDT 24
Finished	Jun 22 04:32:08 PM PDT 24
Peak memory	204004 kb
Host	smart-45f9e170-def1-4281-884a-066a2b5899f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260312847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o utstanding.3260312847
Directory	/workspace/17.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.728867758
Short name	T56
Test name
Test status
Simulation time	87970437 ps
CPU time	2.34 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:07 PM PDT 24
Peak memory	204208 kb
Host	smart-f34b233a-ea15-443d-b5d8-dc221e95ae2a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728867758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.728867758
Directory	/workspace/17.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1564981512
Short name	T85
Test name
Test status
Simulation time	39858194 ps
CPU time	1.83 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:07 PM PDT 24
Peak memory	204352 kb
Host	smart-5c291546-00e7-496f-bb7d-c5a6d1e9604d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564981512 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1564981512
Directory	/workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.1213950948
Short name	T62
Test name
Test status
Simulation time	115322515 ps
CPU time	0.77 seconds
Started	Jun 22 04:32:08 PM PDT 24
Finished	Jun 22 04:32:09 PM PDT 24
Peak memory	204036 kb
Host	smart-f9728e05-ced0-467d-983b-a112453889c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213950948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1213950948
Directory	/workspace/18.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_intr_test.900248181
Short name	T74
Test name
Test status
Simulation time	73921050 ps
CPU time	0.74 seconds
Started	Jun 22 04:32:07 PM PDT 24
Finished	Jun 22 04:32:08 PM PDT 24
Peak memory	204004 kb
Host	smart-40a804c9-a00c-4c44-b75e-b0bbe6a451a0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900248181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.900248181
Directory	/workspace/18.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.898419409
Short name	T154
Test name
Test status
Simulation time	107759619 ps
CPU time	0.85 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	203972 kb
Host	smart-116dc1b4-08a6-4cce-8418-0aa33a8472c8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898419409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou tstanding.898419409
Directory	/workspace/18.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.4219970463
Short name	T133
Test name
Test status
Simulation time	129095972 ps
CPU time	1.85 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	203020 kb
Host	smart-ff8853c8-414f-447e-bb30-a29d0bd76e65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219970463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.4219970463
Directory	/workspace/18.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3394994711
Short name	T25
Test name
Test status
Simulation time	153438256 ps
CPU time	1.54 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204252 kb
Host	smart-f249d109-876b-4705-b068-f1bf18461c61
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394994711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3394994711
Directory	/workspace/18.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2098228367
Short name	T115
Test name
Test status
Simulation time	43108783 ps
CPU time	0.65 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	202856 kb
Host	smart-ec4cc8fc-e23a-47c1-b795-390057af8507
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098228367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2098228367
Directory	/workspace/19.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_intr_test.2243392810
Short name	T104
Test name
Test status
Simulation time	18575789 ps
CPU time	0.67 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:02 PM PDT 24
Peak memory	204128 kb
Host	smart-4d1acb34-521b-4525-a612-ec2fda734bce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243392810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2243392810
Directory	/workspace/19.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1885602581
Short name	T86
Test name
Test status
Simulation time	170855932 ps
CPU time	1.14 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	204260 kb
Host	smart-c3ae8a02-b3c9-4f33-93c2-0bdf7eb91766
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885602581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.1885602581
Directory	/workspace/19.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2754790907
Short name	T140
Test name
Test status
Simulation time	1214390339 ps
CPU time	2.55 seconds
Started	Jun 22 04:32:01 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	204288 kb
Host	smart-21f19d48-06cd-441e-8d78-97529e289c61
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754790907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2754790907
Directory	/workspace/19.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.967307318
Short name	T1
Test name
Test status
Simulation time	52356072 ps
CPU time	1.5 seconds
Started	Jun 22 04:32:00 PM PDT 24
Finished	Jun 22 04:32:02 PM PDT 24
Peak memory	204300 kb
Host	smart-ee03a588-1ca4-4207-be59-a14c8ea7b546
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967307318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.967307318
Directory	/workspace/19.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3025966426
Short name	T29
Test name
Test status
Simulation time	189848677 ps
CPU time	1.24 seconds
Started	Jun 22 04:31:41 PM PDT 24
Finished	Jun 22 04:31:44 PM PDT 24
Peak memory	204280 kb
Host	smart-2b050837-e5fe-41e3-98d0-a17b94492918
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025966426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3025966426
Directory	/workspace/2.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3937135563
Short name	T26
Test name
Test status
Simulation time	74509465 ps
CPU time	3.04 seconds
Started	Jun 22 04:31:42 PM PDT 24
Finished	Jun 22 04:31:46 PM PDT 24
Peak memory	204372 kb
Host	smart-c2f2dc39-0b75-4f2c-ac2e-f1069ee86d3b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937135563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3937135563
Directory	/workspace/2.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1978064125
Short name	T137
Test name
Test status
Simulation time	42202624 ps
CPU time	0.75 seconds
Started	Jun 22 04:31:43 PM PDT 24
Finished	Jun 22 04:31:44 PM PDT 24
Peak memory	204096 kb
Host	smart-dbddd7ba-32cc-40ef-928d-8a281203ced8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978064125 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1978064125
Directory	/workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.3853912427
Short name	T2
Test name
Test status
Simulation time	50005422 ps
CPU time	0.85 seconds
Started	Jun 22 04:31:44 PM PDT 24
Finished	Jun 22 04:31:46 PM PDT 24
Peak memory	204032 kb
Host	smart-cc0a7347-d5a3-4389-8d64-338fcf76e5cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853912427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3853912427
Directory	/workspace/2.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_intr_test.3851764434
Short name	T139
Test name
Test status
Simulation time	22104682 ps
CPU time	0.66 seconds
Started	Jun 22 04:31:45 PM PDT 24
Finished	Jun 22 04:31:48 PM PDT 24
Peak memory	204080 kb
Host	smart-33639b5e-f741-4f30-bc70-80de45119f94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851764434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3851764434
Directory	/workspace/2.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3620709740
Short name	T46
Test name
Test status
Simulation time	657729865 ps
CPU time	0.9 seconds
Started	Jun 22 04:31:44 PM PDT 24
Finished	Jun 22 04:31:46 PM PDT 24
Peak memory	204004 kb
Host	smart-9b984680-9eed-439c-9285-10c6ea9899b4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620709740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.3620709740
Directory	/workspace/2.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3027066995
Short name	T95
Test name
Test status
Simulation time	35030237 ps
CPU time	1.74 seconds
Started	Jun 22 04:31:46 PM PDT 24
Finished	Jun 22 04:31:49 PM PDT 24
Peak memory	204304 kb
Host	smart-b3aadfd0-bf4c-42af-a2c4-8030117c8839
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027066995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3027066995
Directory	/workspace/2.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.454036415
Short name	T150
Test name
Test status
Simulation time	61787235 ps
CPU time	1.52 seconds
Started	Jun 22 04:31:46 PM PDT 24
Finished	Jun 22 04:31:49 PM PDT 24
Peak memory	204304 kb
Host	smart-1ed16be8-b662-4df9-b2ed-01eec3b91af0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454036415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.454036415
Directory	/workspace/2.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.i2c_intr_test.3032698966
Short name	T69
Test name
Test status
Simulation time	118582258 ps
CPU time	0.69 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:04 PM PDT 24
Peak memory	204008 kb
Host	smart-7d06acaf-dd3f-41e7-beb2-1e33cab09a53
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032698966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3032698966
Directory	/workspace/20.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3891046214
Short name	T79
Test name
Test status
Simulation time	49099236 ps
CPU time	0.61 seconds
Started	Jun 22 04:31:59 PM PDT 24
Finished	Jun 22 04:32:00 PM PDT 24
Peak memory	204000 kb
Host	smart-0aec7875-c252-4e20-a095-bda145618af2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891046214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3891046214
Directory	/workspace/21.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.i2c_intr_test.114288490
Short name	T92
Test name
Test status
Simulation time	16011939 ps
CPU time	0.75 seconds
Started	Jun 22 04:32:03 PM PDT 24
Finished	Jun 22 04:32:06 PM PDT 24
Peak memory	203944 kb
Host	smart-1e91965c-4de3-44f8-a283-99edb179b4e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114288490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.114288490
Directory	/workspace/22.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.i2c_intr_test.617326154
Short name	T80
Test name
Test status
Simulation time	55644297 ps
CPU time	0.74 seconds
Started	Jun 22 04:32:02 PM PDT 24
Finished	Jun 22 04:32:05 PM PDT 24
Peak memory	203940 kb
Host	smart-2e81845c-4048-4529-ab7e-9930b379723b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617326154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.617326154
Directory	/workspace/23.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.i2c_intr_test.405218749
Short name	T99
Test name
Test status
Simulation time	19716526 ps
CPU time	0.73 seconds
Started	Jun 22 04:32:11 PM PDT 24
Finished	Jun 22 04:32:13 PM PDT 24
Peak memory	204004 kb
Host	smart-20d67ff1-2584-4a31-bc85-69b450819ba5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405218749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.405218749
Directory	/workspace/24.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.i2c_intr_test.4043086185
Short name	T134
Test name
Test status
Simulation time	31982101 ps
CPU time	0.69 seconds
Started	Jun 22 04:32:11 PM PDT 24
Finished	Jun 22 04:32:13 PM PDT 24
Peak memory	203996 kb
Host	smart-efaf4756-bcb5-4c12-a57c-74cb88086d2d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043086185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.4043086185
Directory	/workspace/27.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3615045547
Short name	T102
Test name
Test status
Simulation time	35828952 ps
CPU time	0.65 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:11 PM PDT 24
Peak memory	204008 kb
Host	smart-cdb08023-9082-4778-b819-aabbb68a2d06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615045547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3615045547
Directory	/workspace/28.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.i2c_intr_test.3744238491
Short name	T9
Test name
Test status
Simulation time	41087711 ps
CPU time	0.63 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:12 PM PDT 24
Peak memory	204096 kb
Host	smart-a73d6667-e09e-4635-87e4-71b06af9406a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744238491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3744238491
Directory	/workspace/29.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3170755602
Short name	T32
Test name
Test status
Simulation time	78511937 ps
CPU time	1.51 seconds
Started	Jun 22 04:31:44 PM PDT 24
Finished	Jun 22 04:31:46 PM PDT 24
Peak memory	204292 kb
Host	smart-2968f0cc-02b3-4721-b463-8345cac2fe42
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170755602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3170755602
Directory	/workspace/3.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2653751734
Short name	T47
Test name
Test status
Simulation time	331585838 ps
CPU time	3.33 seconds
Started	Jun 22 04:31:45 PM PDT 24
Finished	Jun 22 04:31:49 PM PDT 24
Peak memory	204356 kb
Host	smart-35e8f15a-6d29-498c-b1ff-9118e861aab3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653751734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2653751734
Directory	/workspace/3.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2074807788
Short name	T36
Test name
Test status
Simulation time	21492617 ps
CPU time	0.72 seconds
Started	Jun 22 04:31:48 PM PDT 24
Finished	Jun 22 04:31:49 PM PDT 24
Peak memory	204000 kb
Host	smart-53100eeb-fa7e-47cf-8434-b426d33eeac0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074807788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2074807788
Directory	/workspace/3.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1986473256
Short name	T119
Test name
Test status
Simulation time	29176677 ps
CPU time	1.31 seconds
Started	Jun 22 04:31:53 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204404 kb
Host	smart-b03dc3f8-ac8a-4365-89a2-4b28deb7e921
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986473256 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1986473256
Directory	/workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.1030849281
Short name	T124
Test name
Test status
Simulation time	17788172 ps
CPU time	0.68 seconds
Started	Jun 22 04:31:49 PM PDT 24
Finished	Jun 22 04:31:51 PM PDT 24
Peak memory	204056 kb
Host	smart-499b6004-bace-4b74-932e-b18e20be3d98
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030849281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1030849281
Directory	/workspace/3.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_intr_test.415259888
Short name	T109
Test name
Test status
Simulation time	29419611 ps
CPU time	0.67 seconds
Started	Jun 22 04:31:50 PM PDT 24
Finished	Jun 22 04:31:52 PM PDT 24
Peak memory	204008 kb
Host	smart-eb2b3ef2-70b6-4da0-8733-c12b04eb0ebe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415259888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.415259888
Directory	/workspace/3.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2399420914
Short name	T110
Test name
Test status
Simulation time	124363212 ps
CPU time	0.97 seconds
Started	Jun 22 04:31:42 PM PDT 24
Finished	Jun 22 04:31:44 PM PDT 24
Peak memory	204036 kb
Host	smart-ab8a0542-3c35-49d3-92be-992dcb23d7a8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399420914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.2399420914
Directory	/workspace/3.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2832269277
Short name	T112
Test name
Test status
Simulation time	128774024 ps
CPU time	2.38 seconds
Started	Jun 22 04:31:44 PM PDT 24
Finished	Jun 22 04:31:47 PM PDT 24
Peak memory	204308 kb
Host	smart-836006bb-f4ce-458d-bffc-a58172c8edf1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832269277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2832269277
Directory	/workspace/3.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/32.i2c_intr_test.3364750919
Short name	T64
Test name
Test status
Simulation time	29739107 ps
CPU time	0.68 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:12 PM PDT 24
Peak memory	204000 kb
Host	smart-0b0d47eb-c387-49d8-9b98-994bcfe38bf6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364750919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3364750919
Directory	/workspace/32.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.i2c_intr_test.50034498
Short name	T151
Test name
Test status
Simulation time	158597907 ps
CPU time	0.67 seconds
Started	Jun 22 04:32:09 PM PDT 24
Finished	Jun 22 04:32:10 PM PDT 24
Peak memory	204388 kb
Host	smart-a9e22d39-683a-4518-9434-dc2d9939df57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50034498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.50034498
Directory	/workspace/34.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.i2c_intr_test.1195980829
Short name	T108
Test name
Test status
Simulation time	31024285 ps
CPU time	0.74 seconds
Started	Jun 22 04:32:12 PM PDT 24
Finished	Jun 22 04:32:14 PM PDT 24
Peak memory	204008 kb
Host	smart-e004e902-2e2a-4796-b8c1-aafb468c3082
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195980829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1195980829
Directory	/workspace/35.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.i2c_intr_test.2564688230
Short name	T40
Test name
Test status
Simulation time	125471338 ps
CPU time	0.78 seconds
Started	Jun 22 04:32:13 PM PDT 24
Finished	Jun 22 04:32:14 PM PDT 24
Peak memory	204124 kb
Host	smart-7992f638-6369-4cdc-9964-3fae649a1011
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564688230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2564688230
Directory	/workspace/36.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.i2c_intr_test.2474765444
Short name	T94
Test name
Test status
Simulation time	20345923 ps
CPU time	0.72 seconds
Started	Jun 22 04:32:11 PM PDT 24
Finished	Jun 22 04:32:13 PM PDT 24
Peak memory	204000 kb
Host	smart-efa970f3-acfd-499b-9b97-515c4632608c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474765444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2474765444
Directory	/workspace/37.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.i2c_intr_test.3894436059
Short name	T152
Test name
Test status
Simulation time	37307466 ps
CPU time	0.68 seconds
Started	Jun 22 04:32:11 PM PDT 24
Finished	Jun 22 04:32:13 PM PDT 24
Peak memory	204004 kb
Host	smart-12bde67e-15df-44ef-83f9-29092666b196
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894436059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3894436059
Directory	/workspace/38.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.i2c_intr_test.3395892514
Short name	T142
Test name
Test status
Simulation time	32271380 ps
CPU time	0.65 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:11 PM PDT 24
Peak memory	203968 kb
Host	smart-66b2c84c-2dad-4c5a-b7b1-f8916227fa4e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395892514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3395892514
Directory	/workspace/39.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1955851913
Short name	T42
Test name
Test status
Simulation time	47204293 ps
CPU time	2.01 seconds
Started	Jun 22 04:31:54 PM PDT 24
Finished	Jun 22 04:31:57 PM PDT 24
Peak memory	204224 kb
Host	smart-3f587117-d9d9-45d8-857b-0e05b5efbdc4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955851913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1955851913
Directory	/workspace/4.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.536206186
Short name	T106
Test name
Test status
Simulation time	903308937 ps
CPU time	3.14 seconds
Started	Jun 22 04:31:51 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204284 kb
Host	smart-7197543d-e29a-43f5-9f9b-289446f4a7d4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536206186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.536206186
Directory	/workspace/4.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2999894567
Short name	T33
Test name
Test status
Simulation time	77747496 ps
CPU time	0.78 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204012 kb
Host	smart-0d2be220-444d-4e9a-ac7e-5c9dd835b097
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999894567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2999894567
Directory	/workspace/4.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.222234853
Short name	T129
Test name
Test status
Simulation time	142534830 ps
CPU time	1 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204096 kb
Host	smart-f0e10cb4-bb35-4b4f-bfdc-379e10802cbf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222234853 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.222234853
Directory	/workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.3140077641
Short name	T158
Test name
Test status
Simulation time	75428630 ps
CPU time	0.68 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204148 kb
Host	smart-93726ef4-824d-4dc9-b8a7-d1110aca5743
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140077641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3140077641
Directory	/workspace/4.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_intr_test.3091677717
Short name	T6
Test name
Test status
Simulation time	23831036 ps
CPU time	0.68 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:53 PM PDT 24
Peak memory	203944 kb
Host	smart-07e32657-ef27-45dc-8478-f8be7eb5093d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091677717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3091677717
Directory	/workspace/4.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3163126495
Short name	T28
Test name
Test status
Simulation time	156012432 ps
CPU time	2.31 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204252 kb
Host	smart-992d890c-202b-4eb3-bc0b-782fa5f59f6c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163126495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3163126495
Directory	/workspace/4.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.404247857
Short name	T136
Test name
Test status
Simulation time	166582589 ps
CPU time	2.2 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204240 kb
Host	smart-1bac70ef-92c1-47cd-b72d-80f386f246dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404247857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.404247857
Directory	/workspace/4.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.i2c_intr_test.469482711
Short name	T147
Test name
Test status
Simulation time	41529639 ps
CPU time	0.69 seconds
Started	Jun 22 04:32:07 PM PDT 24
Finished	Jun 22 04:32:09 PM PDT 24
Peak memory	204128 kb
Host	smart-2eae66a8-989b-4bda-bd09-31360e07cc4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469482711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.469482711
Directory	/workspace/40.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1918186366
Short name	T98
Test name
Test status
Simulation time	15814456 ps
CPU time	0.67 seconds
Started	Jun 22 04:32:13 PM PDT 24
Finished	Jun 22 04:32:15 PM PDT 24
Peak memory	204004 kb
Host	smart-841cf572-0f08-4211-93cf-472eb9a34732
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918186366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1918186366
Directory	/workspace/41.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.i2c_intr_test.996763925
Short name	T111
Test name
Test status
Simulation time	53040373 ps
CPU time	0.66 seconds
Started	Jun 22 04:32:12 PM PDT 24
Finished	Jun 22 04:32:14 PM PDT 24
Peak memory	203972 kb
Host	smart-fe0efb4c-8dd7-4b0f-9cdd-bf233a5dee86
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996763925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.996763925
Directory	/workspace/42.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.i2c_intr_test.788649804
Short name	T12
Test name
Test status
Simulation time	35522287 ps
CPU time	0.72 seconds
Started	Jun 22 04:32:12 PM PDT 24
Finished	Jun 22 04:32:14 PM PDT 24
Peak memory	203940 kb
Host	smart-dd55a778-92b7-431b-a92a-cde704ef6505
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788649804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.788649804
Directory	/workspace/43.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.i2c_intr_test.290085800
Short name	T91
Test name
Test status
Simulation time	21919355 ps
CPU time	0.73 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:11 PM PDT 24
Peak memory	203952 kb
Host	smart-f057c595-98f1-47e7-8b34-5d50903b0976
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290085800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.290085800
Directory	/workspace/44.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.i2c_intr_test.91647227
Short name	T73
Test name
Test status
Simulation time	62763765 ps
CPU time	0.7 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:12 PM PDT 24
Peak memory	204008 kb
Host	smart-a623dfda-a7f4-4845-a041-3be0239f588d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91647227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.91647227
Directory	/workspace/45.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.i2c_intr_test.3032890077
Short name	T67
Test name
Test status
Simulation time	14805818 ps
CPU time	0.66 seconds
Started	Jun 22 04:32:10 PM PDT 24
Finished	Jun 22 04:32:11 PM PDT 24
Peak memory	203964 kb
Host	smart-28503d34-484f-4a4d-8cc9-1c91fac04680
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032890077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3032890077
Directory	/workspace/46.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.i2c_intr_test.2248004029
Short name	T82
Test name
Test status
Simulation time	38386796 ps
CPU time	0.67 seconds
Started	Jun 22 04:32:11 PM PDT 24
Finished	Jun 22 04:32:13 PM PDT 24
Peak memory	204004 kb
Host	smart-8d0285b8-3902-4dc4-9ec5-22628deb64b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248004029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2248004029
Directory	/workspace/47.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.i2c_intr_test.883895474
Short name	T128
Test name
Test status
Simulation time	42487952 ps
CPU time	0.64 seconds
Started	Jun 22 04:32:12 PM PDT 24
Finished	Jun 22 04:32:14 PM PDT 24
Peak memory	204004 kb
Host	smart-02a3a578-9475-45bb-a369-38949ddeee51
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883895474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.883895474
Directory	/workspace/48.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.i2c_intr_test.1528817879
Short name	T156
Test name
Test status
Simulation time	48832659 ps
CPU time	0.65 seconds
Started	Jun 22 04:32:07 PM PDT 24
Finished	Jun 22 04:32:09 PM PDT 24
Peak memory	204008 kb
Host	smart-67298771-20a1-4a57-8624-bf8bdd7f69b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528817879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1528817879
Directory	/workspace/49.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3717501453
Short name	T160
Test name
Test status
Simulation time	38168610 ps
CPU time	0.99 seconds
Started	Jun 22 04:31:51 PM PDT 24
Finished	Jun 22 04:31:53 PM PDT 24
Peak memory	204096 kb
Host	smart-9e39ea89-591d-41a3-b54a-4afedd38937d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717501453 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3717501453
Directory	/workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.2359092456
Short name	T35
Test name
Test status
Simulation time	175683559 ps
CPU time	0.65 seconds
Started	Jun 22 04:32:32 PM PDT 24
Finished	Jun 22 04:32:33 PM PDT 24
Peak memory	204024 kb
Host	smart-13143e85-de98-49e4-93da-303079c2939f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359092456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2359092456
Directory	/workspace/5.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_intr_test.1272116758
Short name	T114
Test name
Test status
Simulation time	61020637 ps
CPU time	0.66 seconds
Started	Jun 22 04:31:51 PM PDT 24
Finished	Jun 22 04:31:53 PM PDT 24
Peak memory	204008 kb
Host	smart-9237ab52-bf47-4829-a440-7eef4dfbdfc3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272116758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1272116758
Directory	/workspace/5.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.737356276
Short name	T31
Test name
Test status
Simulation time	65720330 ps
CPU time	0.82 seconds
Started	Jun 22 04:31:49 PM PDT 24
Finished	Jun 22 04:31:51 PM PDT 24
Peak memory	203980 kb
Host	smart-5caa0dcd-5060-481f-839b-dcfc8bb77f13
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737356276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_out standing.737356276
Directory	/workspace/5.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.761447860
Short name	T141
Test name
Test status
Simulation time	88348707 ps
CPU time	2.49 seconds
Started	Jun 22 04:31:49 PM PDT 24
Finished	Jun 22 04:31:53 PM PDT 24
Peak memory	204300 kb
Host	smart-68eb597d-3564-4295-b00e-c45368be5182
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761447860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.761447860
Directory	/workspace/5.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3135823634
Short name	T55
Test name
Test status
Simulation time	166428568 ps
CPU time	1.55 seconds
Started	Jun 22 04:31:55 PM PDT 24
Finished	Jun 22 04:31:57 PM PDT 24
Peak memory	204276 kb
Host	smart-5538baa3-e904-4b5e-994f-354076b43ce7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135823634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3135823634
Directory	/workspace/5.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2774257763
Short name	T77
Test name
Test status
Simulation time	85239126 ps
CPU time	1.24 seconds
Started	Jun 22 04:31:51 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204424 kb
Host	smart-40744b56-c4eb-4516-9cd0-cb3536221f85
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774257763 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2774257763
Directory	/workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.773136655
Short name	T7
Test name
Test status
Simulation time	25702988 ps
CPU time	0.78 seconds
Started	Jun 22 04:31:56 PM PDT 24
Finished	Jun 22 04:31:57 PM PDT 24
Peak memory	204036 kb
Host	smart-bfad484d-abfa-40e2-8e03-a2a4dca4cf55
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773136655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.773136655
Directory	/workspace/6.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_intr_test.3545567356
Short name	T148
Test name
Test status
Simulation time	52397861 ps
CPU time	0.67 seconds
Started	Jun 22 04:31:54 PM PDT 24
Finished	Jun 22 04:31:56 PM PDT 24
Peak memory	204024 kb
Host	smart-d06af3e4-f598-4ef7-82ee-b9c39d2aee59
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545567356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3545567356
Directory	/workspace/6.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2690227915
Short name	T30
Test name
Test status
Simulation time	53827456 ps
CPU time	0.85 seconds
Started	Jun 22 04:31:53 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204328 kb
Host	smart-6b7c8ec2-0563-4b62-a023-a3d3ba2c776b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690227915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.2690227915
Directory	/workspace/6.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2025695999
Short name	T123
Test name
Test status
Simulation time	325916376 ps
CPU time	1.54 seconds
Started	Jun 22 04:31:50 PM PDT 24
Finished	Jun 22 04:31:52 PM PDT 24
Peak memory	204228 kb
Host	smart-4c58c1d7-cc17-4994-aec0-dccde5cc9fed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025695999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2025695999
Directory	/workspace/6.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.598975490
Short name	T149
Test name
Test status
Simulation time	39344910 ps
CPU time	0.98 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204096 kb
Host	smart-8b7584cc-bb7d-495e-a4fb-7f7dc1394441
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598975490 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.598975490
Directory	/workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1840760288
Short name	T117
Test name
Test status
Simulation time	57477260 ps
CPU time	0.7 seconds
Started	Jun 22 04:31:51 PM PDT 24
Finished	Jun 22 04:31:53 PM PDT 24
Peak memory	203980 kb
Host	smart-18453f9f-a46e-442b-acdb-9ea81f7856e6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840760288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1840760288
Directory	/workspace/7.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_intr_test.1083959650
Short name	T162
Test name
Test status
Simulation time	59904942 ps
CPU time	0.65 seconds
Started	Jun 22 04:31:53 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204008 kb
Host	smart-c167125d-9408-4e98-af19-71ae126a4589
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083959650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1083959650
Directory	/workspace/7.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2358486756
Short name	T89
Test name
Test status
Simulation time	136771844 ps
CPU time	1.12 seconds
Started	Jun 22 04:31:50 PM PDT 24
Finished	Jun 22 04:31:53 PM PDT 24
Peak memory	204272 kb
Host	smart-fbeca34e-62ff-4164-ae48-0f9d9014fac2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358486756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.2358486756
Directory	/workspace/7.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.4198695069
Short name	T125
Test name
Test status
Simulation time	45615065 ps
CPU time	1.22 seconds
Started	Jun 22 04:31:56 PM PDT 24
Finished	Jun 22 04:31:58 PM PDT 24
Peak memory	204308 kb
Host	smart-aed372a0-b376-43ef-bd2e-7d7ca7a05afd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198695069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4198695069
Directory	/workspace/7.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3920382394
Short name	T130
Test name
Test status
Simulation time	23985598 ps
CPU time	0.87 seconds
Started	Jun 22 04:31:55 PM PDT 24
Finished	Jun 22 04:31:57 PM PDT 24
Peak memory	204096 kb
Host	smart-66fbd02f-bf89-41db-af21-cbf99b6acb89
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920382394 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3920382394
Directory	/workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2794181108
Short name	T105
Test name
Test status
Simulation time	50774986 ps
CPU time	0.74 seconds
Started	Jun 22 04:31:53 PM PDT 24
Finished	Jun 22 04:31:55 PM PDT 24
Peak memory	204032 kb
Host	smart-024a4cd7-c891-48b6-9c1a-e427310ed888
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794181108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2794181108
Directory	/workspace/8.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_intr_test.519892491
Short name	T68
Test name
Test status
Simulation time	16996414 ps
CPU time	0.74 seconds
Started	Jun 22 04:31:53 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204000 kb
Host	smart-7755baf9-bd41-49ae-9484-a57fb5622d56
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519892491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.519892491
Directory	/workspace/8.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.4170601693
Short name	T145
Test name
Test status
Simulation time	322127327 ps
CPU time	1.86 seconds
Started	Jun 22 04:31:55 PM PDT 24
Finished	Jun 22 04:31:58 PM PDT 24
Peak memory	204264 kb
Host	smart-35ac4273-ba01-4c56-9427-b621554cf0af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170601693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.4170601693
Directory	/workspace/8.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.191441332
Short name	T90
Test name
Test status
Simulation time	342249782 ps
CPU time	2.13 seconds
Started	Jun 22 04:31:50 PM PDT 24
Finished	Jun 22 04:31:53 PM PDT 24
Peak memory	204280 kb
Host	smart-3d1dcf1b-e369-4f1f-b4a8-b952da740184
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191441332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.191441332
Directory	/workspace/8.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3359473566
Short name	T107
Test name
Test status
Simulation time	192550376 ps
CPU time	0.87 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204096 kb
Host	smart-7d65f29b-edaf-4ae8-ae6c-b0621a7d3872
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359473566 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3359473566
Directory	/workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.589272532
Short name	T163
Test name
Test status
Simulation time	87225143 ps
CPU time	0.76 seconds
Started	Jun 22 04:31:52 PM PDT 24
Finished	Jun 22 04:31:54 PM PDT 24
Peak memory	204028 kb
Host	smart-0c486181-6612-4f2e-a66f-b51d36deffb1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589272532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.589272532
Directory	/workspace/9.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_intr_test.2855098661
Short name	T100
Test name
Test status
Simulation time	19741764 ps
CPU time	0.69 seconds
Started	Jun 22 04:31:55 PM PDT 24
Finished	Jun 22 04:31:56 PM PDT 24
Peak memory	204008 kb
Host	smart-85600042-916e-4959-8a98-1db7d28f78b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855098661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2855098661
Directory	/workspace/9.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3402276249
Short name	T101
Test name
Test status
Simulation time	91543244 ps
CPU time	0.91 seconds
Started	Jun 22 04:31:50 PM PDT 24
Finished	Jun 22 04:31:52 PM PDT 24
Peak memory	204036 kb
Host	smart-ecef4fd6-304b-45f0-bd63-2ea257cba8ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402276249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.3402276249
Directory	/workspace/9.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.1253332305
Short name	T157
Test name
Test status
Simulation time	209255722 ps
CPU time	2.34 seconds
Started	Jun 22 04:31:55 PM PDT 24
Finished	Jun 22 04:31:58 PM PDT 24
Peak memory	204264 kb
Host	smart-8222bdb9-7e05-4bde-940c-63ae48c0a19b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253332305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1253332305
Directory	/workspace/9.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.345638599
Short name	T138
Test name
Test status
Simulation time	271471152 ps
CPU time	2.5 seconds
Started	Jun 22 04:31:54 PM PDT 24
Finished	Jun 22 04:31:58 PM PDT 24
Peak memory	204268 kb
Host	smart-d3517941-3a03-4b38-b3db-2c541c46c828
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345638599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.345638599
Directory	/workspace/9.i2c_tl_intg_err/latest