Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	345	1			T6	5		T9	5		T14	1
all_pins[1]	345	1			T6	5		T9	5		T14	1
all_pins[2]	345	1			T6	5		T9	5		T14	1
all_pins[3]	345	1			T6	5		T9	5		T14	1
all_pins[4]	345	1			T6	5		T9	5		T14	1
all_pins[5]	345	1			T6	5		T9	5		T14	1
all_pins[6]	345	1			T6	5		T9	5		T14	1
all_pins[7]	345	1			T6	5		T9	5		T14	1
all_pins[8]	345	1			T6	5		T9	5		T14	1
all_pins[9]	345	1			T6	5		T9	5		T14	1
all_pins[10]	345	1			T6	5		T9	5		T14	1
all_pins[11]	345	1			T6	5		T9	5		T14	1
all_pins[12]	345	1			T6	5		T9	5		T14	1
all_pins[13]	345	1			T6	5		T9	5		T14	1
all_pins[14]	345	1			T6	5		T9	5		T14	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4276	1			T6	61		T9	65		T14	15
values[0x1]	899	1			T6	14		T9	10		T10	9
transitions[0x0=>0x1]	669	1			T6	10		T9	7		T10	9
transitions[0x1=>0x0]	680	1			T6	10		T9	7		T10	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	290	1			T6	5		T9	4		T14	1
all_pins[0]	values[0x1]	55	1			T9	1		T10	1		T12	1
all_pins[0]	transitions[0x0=>0x1]	43	1			T10	1		T11	1		T40	1
all_pins[0]	transitions[0x1=>0x0]	43	1			T6	1		T10	1		T11	4
all_pins[1]	values[0x0]	290	1			T6	4		T9	4		T14	1
all_pins[1]	values[0x1]	55	1			T6	1		T9	1		T10	1
all_pins[1]	transitions[0x0=>0x1]	45	1			T9	1		T10	1		T12	1
all_pins[1]	transitions[0x1=>0x0]	35	1			T6	1		T10	1		T13	1
all_pins[2]	values[0x0]	300	1			T6	3		T9	5		T14	1
all_pins[2]	values[0x1]	45	1			T6	2		T10	1		T11	2
all_pins[2]	transitions[0x0=>0x1]	41	1			T6	1		T10	1		T11	2
all_pins[2]	transitions[0x1=>0x0]	44	1			T6	1		T40	1		T13	3
all_pins[3]	values[0x0]	297	1			T6	3		T9	5		T14	1
all_pins[3]	values[0x1]	48	1			T6	2		T40	2		T13	3
all_pins[3]	transitions[0x0=>0x1]	39	1			T6	2		T40	1		T13	2
all_pins[3]	transitions[0x1=>0x0]	55	1			T6	1		T10	1		T11	2
all_pins[4]	values[0x0]	281	1			T6	4		T9	5		T14	1
all_pins[4]	values[0x1]	64	1			T6	1		T10	1		T11	2
all_pins[4]	transitions[0x0=>0x1]	45	1			T6	1		T10	1		T11	2
all_pins[4]	transitions[0x1=>0x0]	55	1			T9	2		T10	2		T11	4
all_pins[5]	values[0x0]	271	1			T6	5		T9	3		T14	1
all_pins[5]	values[0x1]	74	1			T9	2		T10	2		T11	4
all_pins[5]	transitions[0x0=>0x1]	60	1			T9	1		T10	2		T11	3
all_pins[5]	transitions[0x1=>0x0]	35	1			T6	1		T9	2		T50	1
all_pins[6]	values[0x0]	296	1			T6	4		T9	2		T14	1
all_pins[6]	values[0x1]	49	1			T6	1		T9	3		T11	1
all_pins[6]	transitions[0x0=>0x1]	36	1			T6	1		T9	2		T11	1
all_pins[6]	transitions[0x1=>0x0]	49	1			T6	2		T10	2		T12	4
all_pins[7]	values[0x0]	283	1			T6	3		T9	4		T14	1
all_pins[7]	values[0x1]	62	1			T6	2		T9	1		T10	2
all_pins[7]	transitions[0x0=>0x1]	42	1			T9	1		T10	2		T12	3
all_pins[7]	transitions[0x1=>0x0]	51	1			T40	2		T13	2		T64	3
all_pins[8]	values[0x0]	274	1			T6	3		T9	5		T14	1
all_pins[8]	values[0x1]	71	1			T6	2		T12	1		T40	2
all_pins[8]	transitions[0x0=>0x1]	51	1			T6	2		T12	1		T40	2
all_pins[8]	transitions[0x1=>0x0]	48	1			T9	2		T11	5		T40	1
all_pins[9]	values[0x0]	277	1			T6	5		T9	3		T14	1
all_pins[9]	values[0x1]	68	1			T9	2		T11	5		T40	1
all_pins[9]	transitions[0x0=>0x1]	51	1			T9	2		T11	4		T40	1
all_pins[9]	transitions[0x1=>0x0]	38	1			T10	1		T12	1		T40	1
all_pins[10]	values[0x0]	290	1			T6	5		T9	5		T14	1
all_pins[10]	values[0x1]	55	1			T10	1		T12	1		T11	1
all_pins[10]	transitions[0x0=>0x1]	38	1			T10	1		T12	1		T64	1
all_pins[10]	transitions[0x1=>0x0]	41	1			T6	2		T12	1		T11	1
all_pins[11]	values[0x0]	287	1			T6	3		T9	5		T14	1
all_pins[11]	values[0x1]	58	1			T6	2		T12	1		T11	2
all_pins[11]	transitions[0x0=>0x1]	46	1			T6	2		T11	1		T40	3
all_pins[11]	transitions[0x1=>0x0]	36	1			T12	1		T40	1		T13	1
all_pins[12]	values[0x0]	297	1			T6	5		T9	5		T14	1
all_pins[12]	values[0x1]	48	1			T12	2		T11	1		T40	2
all_pins[12]	transitions[0x0=>0x1]	37	1			T12	2		T11	1		T40	2
all_pins[12]	transitions[0x1=>0x0]	64	1			T6	1		T11	1		T13	1
all_pins[13]	values[0x0]	270	1			T6	4		T9	5		T14	1
all_pins[13]	values[0x1]	75	1			T6	1		T11	1		T13	2
all_pins[13]	transitions[0x0=>0x1]	49	1			T6	1		T13	1		T64	1
all_pins[13]	transitions[0x1=>0x0]	46	1			T11	6		T13	2		T50	3
all_pins[14]	values[0x0]	273	1			T6	5		T9	5		T14	1
all_pins[14]	values[0x1]	72	1			T11	7		T13	3		T50	4
all_pins[14]	transitions[0x0=>0x1]	46	1			T11	5		T13	3		T50	2
all_pins[14]	transitions[0x1=>0x0]	40	1			T9	1		T10	1		T12	1