Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T6	4		T9	4		T10	4
all_values[1]	275	1			T6	4		T9	4		T10	4
all_values[2]	275	1			T6	4		T9	4		T10	4
all_values[3]	275	1			T6	4		T9	4		T10	4
all_values[4]	275	1			T6	4		T9	4		T10	4
all_values[5]	275	1			T6	4		T9	4		T10	4
all_values[6]	275	1			T6	4		T9	4		T10	4
all_values[7]	275	1			T6	4		T9	4		T10	4
all_values[8]	275	1			T6	4		T9	4		T10	4
all_values[9]	275	1			T6	4		T9	4		T10	4
all_values[10]	275	1			T6	4		T9	4		T10	4
all_values[11]	275	1			T6	4		T9	4		T10	4
all_values[12]	275	1			T6	4		T9	4		T10	4
all_values[13]	275	1			T6	4		T9	4		T10	4
all_values[14]	275	1			T6	4		T9	4		T10	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2282

1

T6

25

T9

32

T10

30

auto[1]

1843

1

T6

35

T9

28

T10

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

762

1

T6

14

T9

13

T10

16

auto[1]

3363

1

T6

46

T9

47

T10

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2444

1

T6

35

T9

37

T10

38

auto[1]

1681

1

T6

25

T9

23

T10

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T12	1		T40	2		T13	4
all_values[0]	auto[0]	auto[0]	auto[1]	53	1			T6	2		T9	1		T10	1
all_values[0]	auto[0]	auto[1]	auto[0]	17	1			T6	1		T11	2		T13	1
all_values[0]	auto[0]	auto[1]	auto[1]	55	1			T12	2		T11	2		T50	2
all_values[0]	auto[1]	auto[0]	auto[1]	61	1			T9	1		T10	1		T11	2
all_values[0]	auto[1]	auto[1]	auto[1]	56	1			T6	1		T9	2		T10	2
all_values[1]	auto[0]	auto[0]	auto[0]	23	1			T9	1		T40	1		T50	1
all_values[1]	auto[0]	auto[0]	auto[1]	72	1			T9	1		T10	1		T11	1
all_values[1]	auto[0]	auto[1]	auto[0]	21	1			T10	1		T65	1		T66	1
all_values[1]	auto[0]	auto[1]	auto[1]	58	1			T6	3		T9	1		T12	2
all_values[1]	auto[1]	auto[0]	auto[1]	55	1			T10	1		T12	1		T40	4
all_values[1]	auto[1]	auto[1]	auto[1]	46	1			T6	1		T9	1		T10	1
all_values[2]	auto[0]	auto[0]	auto[0]	28	1			T13	1		T51	1		T65	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T9	1		T10	2		T12	1
all_values[2]	auto[0]	auto[1]	auto[0]	17	1			T12	2		T51	1		T65	1
all_values[2]	auto[0]	auto[1]	auto[1]	48	1			T6	1		T9	1		T10	1
all_values[2]	auto[1]	auto[0]	auto[1]	65	1			T6	1		T9	1		T11	1
all_values[2]	auto[1]	auto[1]	auto[1]	45	1			T6	2		T9	1		T10	1
all_values[3]	auto[0]	auto[0]	auto[0]	46	1			T11	1		T40	2		T64	4
all_values[3]	auto[0]	auto[0]	auto[1]	60	1			T9	1		T10	2		T12	2
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T6	2		T10	1		T12	1
all_values[3]	auto[0]	auto[1]	auto[1]	48	1			T6	1		T9	2		T40	2
all_values[3]	auto[1]	auto[0]	auto[1]	63	1			T9	1		T12	1		T11	4
all_values[3]	auto[1]	auto[1]	auto[1]	33	1			T6	1		T10	1		T11	1
all_values[4]	auto[0]	auto[0]	auto[0]	26	1			T9	1		T11	2		T51	2
all_values[4]	auto[0]	auto[0]	auto[1]	65	1			T6	1		T9	1		T10	2
all_values[4]	auto[0]	auto[1]	auto[0]	13	1			T65	1		T67	1		T66	3
all_values[4]	auto[0]	auto[1]	auto[1]	54	1			T11	2		T13	1		T64	3
all_values[4]	auto[1]	auto[0]	auto[1]	60	1			T6	1		T9	2		T10	2
all_values[4]	auto[1]	auto[1]	auto[1]	57	1			T6	2		T11	3		T40	4
all_values[5]	auto[0]	auto[0]	auto[0]	29	1			T11	1		T13	1		T64	2
all_values[5]	auto[0]	auto[0]	auto[1]	56	1			T6	1		T12	1		T13	1
all_values[5]	auto[0]	auto[1]	auto[0]	16	1			T6	1		T10	2		T12	1
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T9	2		T10	1		T12	1
all_values[5]	auto[1]	auto[0]	auto[1]	61	1			T6	1		T11	2		T40	1
all_values[5]	auto[1]	auto[1]	auto[1]	55	1			T6	1		T9	2		T10	1
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T9	1		T12	3		T64	1
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T6	2		T10	2		T11	3
all_values[6]	auto[0]	auto[1]	auto[0]	18	1			T10	1		T12	1		T40	1
all_values[6]	auto[0]	auto[1]	auto[1]	44	1			T9	1		T40	3		T13	2
all_values[6]	auto[1]	auto[0]	auto[1]	66	1			T11	4		T13	3		T64	2
all_values[6]	auto[1]	auto[1]	auto[1]	41	1			T6	2		T9	2		T10	1
all_values[7]	auto[0]	auto[0]	auto[0]	32	1			T6	2		T10	2		T13	1
all_values[7]	auto[0]	auto[0]	auto[1]	62	1			T9	1		T11	4		T40	1
all_values[7]	auto[0]	auto[1]	auto[0]	22	1			T64	3		T68	1		T69	1
all_values[7]	auto[0]	auto[1]	auto[1]	55	1			T6	1		T9	1		T10	1
all_values[7]	auto[1]	auto[0]	auto[1]	55	1			T9	1		T11	1		T40	2
all_values[7]	auto[1]	auto[1]	auto[1]	49	1			T6	1		T9	1		T10	1
all_values[8]	auto[0]	auto[0]	auto[0]	27	1			T12	1		T50	1		T51	2
all_values[8]	auto[0]	auto[0]	auto[1]	50	1			T6	1		T9	1		T12	1
all_values[8]	auto[0]	auto[1]	auto[0]	19	1			T9	2		T10	4		T51	1
all_values[8]	auto[0]	auto[1]	auto[1]	52	1			T6	1		T11	3		T40	2
all_values[8]	auto[1]	auto[0]	auto[1]	67	1			T6	1		T11	3		T13	5
all_values[8]	auto[1]	auto[1]	auto[1]	60	1			T6	1		T9	1		T12	2
all_values[9]	auto[0]	auto[0]	auto[0]	24	1			T9	1		T12	1		T51	1
all_values[9]	auto[0]	auto[0]	auto[1]	56	1			T6	1		T10	2		T12	1
all_values[9]	auto[0]	auto[1]	auto[0]	17	1			T6	2		T70	2		T71	1
all_values[9]	auto[0]	auto[1]	auto[1]	49	1			T9	1		T12	1		T11	1
all_values[9]	auto[1]	auto[0]	auto[1]	68	1			T9	2		T10	2		T12	1
all_values[9]	auto[1]	auto[1]	auto[1]	61	1			T6	1		T11	5		T40	2
all_values[10]	auto[0]	auto[0]	auto[0]	30	1			T6	1		T40	2		T13	1
all_values[10]	auto[0]	auto[0]	auto[1]	54	1			T9	1		T12	2		T11	1
all_values[10]	auto[0]	auto[1]	auto[0]	19	1			T6	3		T9	1		T10	1
all_values[10]	auto[0]	auto[1]	auto[1]	51	1			T9	1		T10	1		T11	3
all_values[10]	auto[1]	auto[0]	auto[1]	68	1			T9	1		T12	1		T11	2
all_values[10]	auto[1]	auto[1]	auto[1]	53	1			T10	2		T12	1		T11	1
all_values[11]	auto[0]	auto[0]	auto[0]	33	1			T9	1		T13	1		T64	1
all_values[11]	auto[0]	auto[0]	auto[1]	50	1			T9	2		T11	2		T51	1
all_values[11]	auto[0]	auto[1]	auto[0]	28	1			T12	1		T50	4		T51	2
all_values[11]	auto[0]	auto[1]	auto[1]	55	1			T6	1		T10	2		T12	2
all_values[11]	auto[1]	auto[0]	auto[1]	61	1			T6	2		T9	1		T10	2
all_values[11]	auto[1]	auto[1]	auto[1]	48	1			T6	1		T12	1		T11	2
all_values[12]	auto[0]	auto[0]	auto[0]	39	1			T6	1		T10	2		T64	1
all_values[12]	auto[0]	auto[0]	auto[1]	51	1			T6	1		T11	2		T40	3
all_values[12]	auto[0]	auto[1]	auto[0]	16	1			T10	2		T12	1		T50	1
all_values[12]	auto[0]	auto[1]	auto[1]	63	1			T6	1		T9	3		T12	1
all_values[12]	auto[1]	auto[0]	auto[1]	60	1			T6	1		T9	1		T11	1
all_values[12]	auto[1]	auto[1]	auto[1]	46	1			T12	2		T11	2		T40	2
all_values[13]	auto[0]	auto[0]	auto[0]	22	1			T12	2		T50	1		T51	2
all_values[13]	auto[0]	auto[0]	auto[1]	65	1			T6	2		T9	1		T10	1
all_values[13]	auto[0]	auto[1]	auto[0]	27	1			T9	1		T12	2		T11	1
all_values[13]	auto[0]	auto[1]	auto[1]	52	1			T10	2		T40	1		T13	1
all_values[13]	auto[1]	auto[0]	auto[1]	58	1			T6	1		T9	2		T10	1
all_values[13]	auto[1]	auto[1]	auto[1]	51	1			T6	1		T11	2		T13	2
all_values[14]	auto[0]	auto[0]	auto[0]	33	1			T9	3		T12	1		T13	1
all_values[14]	auto[0]	auto[0]	auto[1]	58	1			T6	1		T10	1		T40	2
all_values[14]	auto[0]	auto[1]	auto[0]	21	1			T6	1		T9	1		T40	2
all_values[14]	auto[0]	auto[1]	auto[1]	51	1			T12	2		T11	4		T40	1
all_values[14]	auto[1]	auto[0]	auto[1]	59	1			T6	1		T10	3		T13	1
all_values[14]	auto[1]	auto[1]	auto[1]	53	1			T6	1		T12	1		T11	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal