Summary for Variable cp_sclval
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_sclval
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
387 |
1 |
|
|
T2 |
6 |
|
T73 |
11 |
|
T74 |
6 |
auto[1] |
371 |
1 |
|
|
T2 |
7 |
|
T73 |
7 |
|
T74 |
7 |
Summary for Variable cp_sdaval
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_sdaval
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349 |
1 |
|
|
T2 |
5 |
|
T73 |
11 |
|
T74 |
6 |
auto[1] |
409 |
1 |
|
|
T2 |
8 |
|
T73 |
7 |
|
T74 |
7 |
Summary for Variable cp_txorvden
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_txorvden
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
388 |
1 |
|
|
T2 |
6 |
|
T73 |
11 |
|
T74 |
5 |
auto[1] |
370 |
1 |
|
|
T2 |
7 |
|
T73 |
7 |
|
T74 |
8 |
Summary for Cross cp_txorvden_x_sclval
Samples crossed: cp_txorvden cp_sclval
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_txorvden_x_sclval
Bins
cp_txorvden | cp_sclval | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
203 |
1 |
|
|
T2 |
4 |
|
T73 |
8 |
|
T74 |
2 |
auto[0] |
auto[1] |
185 |
1 |
|
|
T2 |
2 |
|
T73 |
3 |
|
T74 |
3 |
auto[1] |
auto[0] |
184 |
1 |
|
|
T2 |
2 |
|
T73 |
3 |
|
T74 |
4 |
auto[1] |
auto[1] |
186 |
1 |
|
|
T2 |
5 |
|
T73 |
4 |
|
T74 |
4 |
Summary for Cross cp_txorvden_x_sdaval
Samples crossed: cp_txorvden cp_sdaval
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_txorvden_x_sdaval
Bins
cp_txorvden | cp_sdaval | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
170 |
1 |
|
|
T2 |
2 |
|
T73 |
4 |
|
T74 |
2 |
auto[0] |
auto[1] |
218 |
1 |
|
|
T2 |
4 |
|
T73 |
7 |
|
T74 |
3 |
auto[1] |
auto[0] |
179 |
1 |
|
|
T2 |
3 |
|
T73 |
7 |
|
T74 |
4 |
auto[1] |
auto[1] |
191 |
1 |
|
|
T2 |
4 |
|
T74 |
4 |
|
T75 |
5 |