Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	392949806	0	0	0
ctrl_rd_A	392949806	1822	0	0
host_fifo_config_rd_A	392949806	5200	0	0
host_nack_handler_timeout_rd_A	392949806	1217	0	0
host_timeout_ctrl_rd_A	392949806	1077	0	0
intr_enable_rd_A	392949806	3161	0	0
ovrd_rd_A	392949806	1768	0	0
target_fifo_config_rd_A	392949806	1214	0	0
target_id_rd_A	392949806	1522	0	0
target_timeout_ctrl_rd_A	392949806	1085	0	0
timeout_ctrl_rd_A	392949806	1365	0	0
timing0_rd_A	392949806	1114	0	0
timing1_rd_A	392949806	1244	0	0
timing2_rd_A	392949806	1162	0	0
timing3_rd_A	392949806	1209	0	0
timing4_rd_A	392949806	1273	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1822	0	0
T91	6257	64	0	0
T92	2127	5	0	0
T93	6840	117	0	0
T94	2131	20	0	0
T95	2586	44	0	0
T96	7894	156	0	0
T97	11229	17	0	0
T98	1337	2	0	0
T99	5635	28	0	0
T100	11082	114	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	5200	0	0
T12	141534	0	0	0
T18	33561	0	0	0
T23	920108	0	0	0
T36	15480	0	0	0
T56	8694	0	0	0
T67	330330	119	0	0
T73	2824	0	0	0
T101	356073	184	0	0
T102	0	85	0	0
T103	0	562	0	0
T104	0	131	0	0
T105	0	124	0	0
T106	0	68	0	0
T107	0	235	0	0
T108	0	369	0	0
T109	0	140	0	0
T110	18504	0	0	0
T111	1141	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1217	0	0
T91	6257	22	0	0
T92	2127	15	0	0
T93	6840	94	0	0
T94	2131	6	0	0
T95	2586	11	0	0
T96	7894	76	0	0
T98	1337	7	0	0
T99	5635	78	0	0
T100	11082	42	0	0
T112	8383	23	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1077	0	0
T91	6257	67	0	0
T92	2127	8	0	0
T93	6840	89	0	0
T94	2131	11	0	0
T95	2586	8	0	0
T96	7894	42	0	0
T97	11229	16	0	0
T98	1337	1	0	0
T99	5635	31	0	0
T100	11082	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	3161	0	0
T50	471867	1	0	0
T91	0	44	0	0
T92	0	45	0	0
T93	0	106	0	0
T104	679461	12	0	0
T107	0	6	0	0
T108	0	25	0	0
T113	0	13	0	0
T114	0	13	0	0
T115	0	25	0	0
T116	122663	0	0	0
T117	10925	0	0	0
T118	11719	0	0	0
T119	175268	0	0	0
T120	85896	0	0	0
T121	20618	0	0	0
T122	31410	0	0	0
T123	429088	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1768	0	0
T57	16688	0	0	0
T75	2186	94	0	0
T124	0	29	0	0
T125	0	32	0	0
T126	0	15	0	0
T127	0	38	0	0
T128	0	54	0	0
T129	0	42	0	0
T130	0	33	0	0
T131	0	49	0	0
T132	0	23	0	0
T133	16621	0	0	0
T134	1560	0	0	0
T135	20726	0	0	0
T136	24603	0	0	0
T137	13813	0	0	0
T138	7425	0	0	0
T139	119774	0	0	0
T140	2502	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1214	0	0
T91	6257	13	0	0
T92	2127	7	0	0
T93	6840	104	0	0
T94	2131	11	0	0
T95	2586	6	0	0
T96	7894	63	0	0
T97	11229	14	0	0
T98	1337	6	0	0
T99	5635	71	0	0
T100	11082	52	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1522	0	0
T91	6257	28	0	0
T92	2127	25	0	0
T93	6840	101	0	0
T94	2131	10	0	0
T95	2586	24	0	0
T96	7894	66	0	0
T97	11229	7	0	0
T98	1337	3	0	0
T99	5635	32	0	0
T100	11082	100	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1085	0	0
T91	6257	43	0	0
T92	2127	15	0	0
T93	6840	83	0	0
T94	2131	5	0	0
T95	2586	17	0	0
T96	7894	42	0	0
T97	11229	6	0	0
T98	1337	9	0	0
T99	5635	17	0	0
T100	11082	60	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1365	0	0
T91	6257	59	0	0
T92	2127	10	0	0
T93	6840	101	0	0
T94	2131	25	0	0
T95	2586	14	0	0
T96	7894	83	0	0
T98	1337	13	0	0
T99	5635	4	0	0
T100	11082	63	0	0
T112	8383	46	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1114	0	0
T91	6257	43	0	0
T92	2127	21	0	0
T93	6840	80	0	0
T94	2131	5	0	0
T95	2586	11	0	0
T96	7894	55	0	0
T97	11229	6	0	0
T98	1337	1	0	0
T99	5635	30	0	0
T100	11082	50	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1244	0	0
T91	6257	47	0	0
T92	2127	10	0	0
T93	6840	84	0	0
T94	2131	8	0	0
T95	2586	18	0	0
T96	7894	62	0	0
T97	11229	18	0	0
T98	1337	7	0	0
T99	5635	36	0	0
T100	11082	69	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1162	0	0
T91	6257	14	0	0
T92	2127	13	0	0
T93	6840	97	0	0
T94	2131	6	0	0
T95	2586	10	0	0
T96	7894	52	0	0
T97	11229	4	0	0
T98	1337	6	0	0
T99	5635	40	0	0
T100	11082	62	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1209	0	0
T91	6257	55	0	0
T92	2127	10	0	0
T93	6840	99	0	0
T94	2131	8	0	0
T95	2586	12	0	0
T96	7894	58	0	0
T97	11229	19	0	0
T99	5635	31	0	0
T100	11082	52	0	0
T112	8383	26	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392949806	1273	0	0
T91	6257	16	0	0
T92	2127	12	0	0
T93	6840	82	0	0
T94	2131	13	0	0
T95	2586	15	0	0
T96	7894	65	0	0
T97	11229	25	0	0
T98	1337	7	0	0
T99	5635	21	0	0
T100	11082	58	0	0