Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

160417

1

T2

346

T9

447

T33

40

ack

13300

1

T1

16

T2

9

T4

11

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	696	1			T2	3		T9	2		T36	4
high	35772	1			T1	2		T2	78		T4	3
med	64912	1			T1	3		T2	125		T4	1
sml	71635	1			T1	11		T2	145		T4	7
all_zero	702	1			T2	4		T9	1		T33	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86706

1

T1

7

T2

158

T4

7

auto[1]

87011

1

T1

9

T2

197

T4

4

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118946

1

T1

16

T2

235

T4

11

auto[1]

54771

1

T2

120

T9

152

T33

15

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166787

1

T1

8

T2

349

T4

6

auto[1]

6930

1

T1

8

T2

6

T4

5

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164524

1

T1

8

T2

348

T4

5

auto[1]

9193

1

T1

8

T2

7

T4

6

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165499

1

T1

8

T2

352

T4

6

auto[1]

8218

1

T1

8

T2

3

T4

5

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86706

1

T1

7

T2

158

T4

7

auto[1]

87011

1

T1

9

T2

197

T4

4

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118946

1

T1

16

T2

235

T4

11

auto[1]

54771

1

T2

120

T9

152

T33

15

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166787

1

T1

8

T2

349

T4

6

auto[1]

6930

1

T1

8

T2

6

T4

5

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164524

1

T1

8

T2

348

T4

5

auto[1]

9193

1

T1

8

T2

7

T4

6

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165499

1

T1

8

T2

352

T4

6

auto[1]

8218

1

T1

8

T2

3

T4

5

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T109

1

T265

1

T100

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T44

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T98

1

T266

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

265

1

T9

1

T34

1

T36

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

139

1

T2

1

T9

1

T36

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

116

1

T2

1

T36

1

T53

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

520

1

T2

1

T9

2

T34

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

235

1

T9

1

T36

4

T141

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

267

1

T36

4

T53

1

T48

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

526

1

T2

1

T34

1

T36

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

274

1

T34

1

T36

3

T141

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

226

1

T2

1

T9

1

T36

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

9

1

T44

1

T204

1

T267

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

7

1

T139

1

T240

1

T268

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T44

1

T269

1

T270

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	51195	1			T2	94		T9	145		T33	6
write_address_byte	9193	1			T1	8		T2	7		T4	6
read_with_ack	1991	1			T2	3		T9	8		T33	2
read_with_nack	4939	1			T1	8		T2	3		T4	5
stop_byte	8218	1			T1	8		T2	3		T4	5
write_address_byte_nak	4571	1			T2	6		T9	7		T33	4
data_byte_nack	160417	1			T2	346		T9	447		T33	40
stop_byte_nack	5005	1			T2	3		T9	4		T33	4
nakok_byte_nack	80346	1			T2	192		T9	232		T33	26
nakok_addr_byte_nack	2275	1			T2	4		T9	4		T33	4