Summary for Variable address_match
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for address_match
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5791618 |
1 |
|
|
T8 |
11146 |
|
T11 |
5572 |
|
T12 |
20745 |
auto[1] |
14708015 |
1 |
|
|
T1 |
29526 |
|
T2 |
26712 |
|
T3 |
10 |
Summary for Variable cp_address_match
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_address_match
Excluded/Illegal bins
NAME | COUNT | STATUS |
illegal |
0 |
Illegal |
ignore |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_addr_no_match |
2205485 |
1 |
|
|
T8 |
3281 |
|
T12 |
7398 |
|
T17 |
173 |
read_addr_match |
10355724 |
1 |
|
|
T1 |
29505 |
|
T2 |
18136 |
|
T4 |
20281 |
write_addr_no_match |
3378213 |
1 |
|
|
T8 |
5151 |
|
T11 |
5552 |
|
T12 |
13325 |
write_addr_match |
4247500 |
1 |
|
|
T2 |
8555 |
|
T8 |
147 |
|
T9 |
11077 |
Summary for Variable cp_read_byte
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
1 |
4 |
80.00 |
User Defined Bins for cp_read_byte
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_one |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
high |
2535514 |
1 |
|
|
T1 |
6315 |
|
T2 |
3502 |
|
T4 |
3647 |
med |
4859114 |
1 |
|
|
T1 |
11790 |
|
T2 |
7128 |
|
T4 |
7856 |
low |
5034217 |
1 |
|
|
T1 |
11184 |
|
T2 |
7293 |
|
T4 |
8672 |
all_zero |
132364 |
1 |
|
|
T1 |
216 |
|
T2 |
213 |
|
T4 |
106 |
Summary for Variable cp_write_byte
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
1 |
4 |
80.00 |
User Defined Bins for cp_write_byte
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_one |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
high |
1544296 |
1 |
|
|
T2 |
1988 |
|
T8 |
828 |
|
T9 |
2449 |
med |
2963677 |
1 |
|
|
T2 |
3399 |
|
T8 |
2304 |
|
T9 |
4296 |
low |
3041336 |
1 |
|
|
T2 |
3088 |
|
T8 |
2074 |
|
T9 |
4227 |
all_zero |
76404 |
1 |
|
|
T2 |
80 |
|
T8 |
92 |
|
T9 |
105 |
Summary for Variable ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for ip_mode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
device |
6220494 |
1 |
|
|
T8 |
11452 |
|
T11 |
5766 |
|
T12 |
21354 |
host |
14279139 |
1 |
|
|
T1 |
29526 |
|
T2 |
26712 |
|
T3 |
10 |
Summary for Cross cross_address_match_x_ip_mode
Samples crossed: address_match ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_address_match_x_ip_mode
Bins
address_match | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
device |
5791540 |
1 |
|
|
T8 |
11146 |
|
T11 |
5572 |
|
T12 |
20745 |
auto[0] |
host |
78 |
1 |
|
|
T136 |
1 |
|
T137 |
4 |
|
T225 |
2 |
auto[1] |
device |
428954 |
1 |
|
|
T8 |
306 |
|
T11 |
194 |
|
T12 |
609 |
auto[1] |
host |
14279061 |
1 |
|
|
T1 |
29526 |
|
T2 |
26712 |
|
T3 |
10 |
Summary for Cross cross_write_byte_x_ip_mode
Samples crossed: cp_write_byte ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
2 |
8 |
80.00 |
2 |
Automatically Generated Cross Bins for cross_write_byte_x_ip_mode
Element holes
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
[all_one] |
* |
-- |
-- |
2 |
|
Covered bins
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
high |
device |
723383 |
1 |
|
|
T8 |
828 |
|
T11 |
1309 |
|
T12 |
2689 |
high |
host |
820913 |
1 |
|
|
T2 |
1988 |
|
T9 |
2449 |
|
T33 |
119 |
med |
device |
1383212 |
1 |
|
|
T8 |
2304 |
|
T11 |
2195 |
|
T12 |
5325 |
med |
host |
1580465 |
1 |
|
|
T2 |
3399 |
|
T9 |
4296 |
|
T33 |
716 |
low |
device |
1439084 |
1 |
|
|
T8 |
2074 |
|
T11 |
2196 |
|
T12 |
5516 |
low |
host |
1602252 |
1 |
|
|
T2 |
3088 |
|
T9 |
4227 |
|
T33 |
72 |
all_zero |
device |
35439 |
1 |
|
|
T8 |
92 |
|
T11 |
44 |
|
T12 |
168 |
all_zero |
host |
40965 |
1 |
|
|
T2 |
80 |
|
T9 |
105 |
|
T33 |
3 |
Summary for Cross cross_read_byte_x_ip_mode
Samples crossed: cp_write_byte ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
2 |
8 |
80.00 |
2 |
Automatically Generated Cross Bins for cross_read_byte_x_ip_mode
Element holes
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
[all_one] |
* |
-- |
-- |
2 |
|
Covered bins
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
high |
device |
723383 |
1 |
|
|
T8 |
828 |
|
T11 |
1309 |
|
T12 |
2689 |
high |
host |
820913 |
1 |
|
|
T2 |
1988 |
|
T9 |
2449 |
|
T33 |
119 |
med |
device |
1383212 |
1 |
|
|
T8 |
2304 |
|
T11 |
2195 |
|
T12 |
5325 |
med |
host |
1580465 |
1 |
|
|
T2 |
3399 |
|
T9 |
4296 |
|
T33 |
716 |
low |
device |
1439084 |
1 |
|
|
T8 |
2074 |
|
T11 |
2196 |
|
T12 |
5516 |
low |
host |
1602252 |
1 |
|
|
T2 |
3088 |
|
T9 |
4227 |
|
T33 |
72 |
all_zero |
device |
35439 |
1 |
|
|
T8 |
92 |
|
T11 |
44 |
|
T12 |
168 |
all_zero |
host |
40965 |
1 |
|
|
T2 |
80 |
|
T9 |
105 |
|
T33 |
3 |