Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42451785	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9816153

1

T1

9498

T2

4114

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51561566	1			T1	19845		T2	17283		T3	49
values[0x0]	352311	1			T1	88		T2	196		T3	20
values[0x1]	354061	1			T1	88		T2	220		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30256811	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22011127

1

T1

11816

T2

8025

T3

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	177254	1			T1	131		T2	64		T6	329
valid_sources[0x01]	187148	1			T1	73		T2	84		T5	1
valid_sources[0x02]	182281	1			T1	80		T2	51		T5	3
valid_sources[0x03]	182722	1			T1	68		T2	81		T5	2
valid_sources[0x04]	187185	1			T1	99		T2	77		T6	326
valid_sources[0x05]	182144	1			T1	90		T2	93		T6	300
valid_sources[0x06]	300002	1			T1	77		T2	40		T3	95
valid_sources[0x07]	190408	1			T1	56		T2	46		T4	1
valid_sources[0x08]	179252	1			T1	105		T2	32		T6	333
valid_sources[0x09]	190467	1			T1	69		T2	72		T6	339
valid_sources[0x0a]	177747	1			T1	112		T2	62		T6	312
valid_sources[0x0b]	402380	1			T1	92		T2	74		T6	322
valid_sources[0x0c]	184803	1			T1	93		T2	60		T4	1
valid_sources[0x0d]	178945	1			T1	67		T2	68		T6	328
valid_sources[0x0e]	194656	1			T1	91		T2	78		T5	3
valid_sources[0x0f]	183822	1			T1	69		T2	54		T4	1
valid_sources[0x10]	201583	1			T1	107		T2	87		T6	326
valid_sources[0x11]	191520	1			T1	80		T2	61		T6	316
valid_sources[0x12]	188500	1			T1	79		T2	83		T4	2670
valid_sources[0x13]	221696	1			T1	149		T2	61		T6	298
valid_sources[0x14]	187190	1			T1	78		T2	77		T6	333
valid_sources[0x15]	210858	1			T1	64		T2	62		T6	329
valid_sources[0x16]	193660	1			T1	66		T2	72		T6	295
valid_sources[0x17]	181109	1			T1	66		T2	74		T6	295
valid_sources[0x18]	187420	1			T1	99		T2	105		T6	303
valid_sources[0x19]	184276	1			T1	65		T2	67		T6	353
valid_sources[0x1a]	186607	1			T1	93		T2	104		T6	314
valid_sources[0x1b]	185263	1			T1	94		T2	53		T6	264
valid_sources[0x1c]	972525	1			T1	100		T2	53		T6	322
valid_sources[0x1d]	193183	1			T1	45		T2	53		T5	11
valid_sources[0x1e]	204063	1			T1	95		T2	80		T6	328
valid_sources[0x1f]	204319	1			T1	73		T2	90		T5	1
valid_sources[0x20]	185817	1			T1	94		T2	80		T5	1
valid_sources[0x21]	199213	1			T1	72		T2	37		T6	347
valid_sources[0x22]	178278	1			T1	52		T2	94		T6	315
valid_sources[0x23]	200101	1			T1	62		T2	91		T6	318
valid_sources[0x24]	193219	1			T1	117		T2	76		T6	287
valid_sources[0x25]	193547	1			T1	67		T2	64		T5	3
valid_sources[0x26]	190672	1			T1	61		T2	106		T6	277
valid_sources[0x27]	176841	1			T1	74		T2	77		T6	286
valid_sources[0x28]	184234	1			T1	115		T2	56		T6	296
valid_sources[0x29]	197011	1			T1	88		T2	87		T6	295
valid_sources[0x2a]	197810	1			T1	115		T2	46		T6	311
valid_sources[0x2b]	189657	1			T1	52		T2	45		T4	1
valid_sources[0x2c]	183831	1			T1	105		T2	75		T6	330
valid_sources[0x2d]	193135	1			T1	79		T2	66		T6	314
valid_sources[0x2e]	196917	1			T1	78		T2	62		T6	338
valid_sources[0x2f]	189129	1			T1	48		T2	97		T4	1
valid_sources[0x30]	183184	1			T1	101		T2	60		T6	298
valid_sources[0x31]	195126	1			T1	50		T2	53		T5	5
valid_sources[0x32]	189680	1			T1	78		T2	73		T6	329
valid_sources[0x33]	194228	1			T1	65		T2	61		T6	295
valid_sources[0x34]	180097	1			T1	97		T2	116		T6	293
valid_sources[0x35]	304808	1			T1	66		T2	61		T6	307
valid_sources[0x36]	214286	1			T1	75		T2	64		T5	7
valid_sources[0x37]	173267	1			T1	51		T2	57		T6	332
valid_sources[0x38]	181040	1			T1	40		T2	51		T4	2215
valid_sources[0x39]	185301	1			T1	65		T2	99		T6	304
valid_sources[0x3a]	186502	1			T1	61		T2	54		T6	320
valid_sources[0x3b]	180541	1			T1	57		T2	60		T5	1
valid_sources[0x3c]	194125	1			T1	76		T2	78		T6	330
valid_sources[0x3d]	187850	1			T1	75		T2	73		T4	1
valid_sources[0x3e]	184243	1			T1	53		T2	54		T6	314
valid_sources[0x3f]	183190	1			T1	54		T2	60		T6	298
valid_sources[0x40]	183053	1			T1	66		T2	83		T6	306
valid_sources[0x41]	222956	1			T1	91		T2	69		T4	1
valid_sources[0x42]	170709	1			T1	82		T2	51		T6	331
valid_sources[0x43]	221901	1			T1	80		T2	79		T5	1
valid_sources[0x44]	173905	1			T1	87		T2	60		T6	319
valid_sources[0x45]	203644	1			T1	51		T2	64		T5	3
valid_sources[0x46]	181908	1			T1	108		T2	88		T6	311
valid_sources[0x47]	313624	1			T1	75		T2	59		T6	301
valid_sources[0x48]	192937	1			T1	93		T2	75		T6	294
valid_sources[0x49]	223498	1			T1	110		T2	80		T4	1
valid_sources[0x4a]	185447	1			T1	73		T2	64		T6	293
valid_sources[0x4b]	192537	1			T1	55		T2	74		T6	314
valid_sources[0x4c]	179768	1			T1	82		T2	85		T6	301
valid_sources[0x4d]	181623	1			T1	55		T2	62		T5	2
valid_sources[0x4e]	192755	1			T1	67		T2	73		T6	300
valid_sources[0x4f]	192286	1			T1	99		T2	86		T6	315
valid_sources[0x50]	190967	1			T1	59		T2	87		T6	316
valid_sources[0x51]	196053	1			T1	62		T2	58		T4	129
valid_sources[0x52]	181020	1			T1	63		T2	60		T6	283
valid_sources[0x53]	173819	1			T1	37		T2	120		T6	312
valid_sources[0x54]	204115	1			T1	110		T2	71		T6	285
valid_sources[0x55]	189006	1			T1	69		T2	65		T6	299
valid_sources[0x56]	225087	1			T1	90		T2	87		T6	320
valid_sources[0x57]	204572	1			T1	79		T2	125		T6	327
valid_sources[0x58]	189746	1			T1	56		T2	65		T5	1
valid_sources[0x59]	201205	1			T1	54		T2	87		T4	6
valid_sources[0x5a]	195767	1			T1	87		T2	47		T5	5
valid_sources[0x5b]	176436	1			T1	84		T2	59		T6	305
valid_sources[0x5c]	192225	1			T1	130		T2	49		T4	1
valid_sources[0x5d]	174002	1			T1	73		T2	50		T6	331
valid_sources[0x5e]	188620	1			T1	48		T2	86		T5	1
valid_sources[0x5f]	207858	1			T1	92		T2	83		T6	314
valid_sources[0x60]	190351	1			T1	77		T2	79		T5	1
valid_sources[0x61]	362861	1			T1	51		T2	75		T6	310
valid_sources[0x62]	199501	1			T1	90		T2	85		T6	303
valid_sources[0x63]	240442	1			T1	94		T2	81		T6	322
valid_sources[0x64]	208866	1			T1	46		T2	68		T5	1
valid_sources[0x65]	221936	1			T1	80		T2	82		T4	1
valid_sources[0x66]	294777	1			T1	102		T2	77		T6	332
valid_sources[0x67]	306886	1			T1	95		T2	55		T4	1
valid_sources[0x68]	196785	1			T1	43		T2	80		T5	6
valid_sources[0x69]	202908	1			T1	138		T2	129		T6	292
valid_sources[0x6a]	181544	1			T1	77		T2	57		T6	324
valid_sources[0x6b]	193632	1			T1	61		T2	40		T5	2
valid_sources[0x6c]	185444	1			T1	62		T2	98		T6	305
valid_sources[0x6d]	213386	1			T1	51		T2	78		T6	323
valid_sources[0x6e]	285351	1			T1	80		T2	41		T5	7
valid_sources[0x6f]	178067	1			T1	79		T2	59		T5	2
valid_sources[0x70]	183627	1			T1	77		T2	42		T6	315
valid_sources[0x71]	211647	1			T1	90		T2	46		T6	317
valid_sources[0x72]	193775	1			T1	84		T2	68		T6	317
valid_sources[0x73]	190564	1			T1	59		T2	62		T6	278
valid_sources[0x74]	201178	1			T1	98		T2	60		T5	2
valid_sources[0x75]	192884	1			T1	111		T2	76		T6	344
valid_sources[0x76]	197056	1			T1	66		T2	81		T6	338
valid_sources[0x77]	200414	1			T1	77		T2	93		T6	303
valid_sources[0x78]	186788	1			T1	81		T2	35		T5	4
valid_sources[0x79]	226386	1			T1	73		T2	77		T5	2
valid_sources[0x7a]	187881	1			T1	85		T2	98		T6	315
valid_sources[0x7b]	199930	1			T1	97		T2	38		T5	1
valid_sources[0x7c]	292286	1			T1	47		T2	79		T6	326
valid_sources[0x7d]	186430	1			T1	43		T2	65		T4	1444
valid_sources[0x7e]	281655	1			T1	57		T2	63		T6	342
valid_sources[0x7f]	184534	1			T1	88		T2	66		T6	309
valid_sources[0x80]	184298	1			T1	46		T2	51		T6	319

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9476601

1

T1

9351

T2

3936

T3

1

values[0x0]

all_enables

biggest_size

196279

1

T1

76

T2

102

T3

9

values[0x1]

all_enables

biggest_size

143273

1

T1

71

T2

76

T3

4