Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	381367195	0	0	0
ctrl_rd_A	381367195	1379	0	0
host_fifo_config_rd_A	381367195	5204	0	0
host_nack_handler_timeout_rd_A	381367195	766	0	0
host_timeout_ctrl_rd_A	381367195	721	0	0
intr_enable_rd_A	381367195	2711	0	0
ovrd_rd_A	381367195	1480	0	0
target_fifo_config_rd_A	381367195	758	0	0
target_id_rd_A	381367195	999	0	0
target_timeout_ctrl_rd_A	381367195	748	0	0
timeout_ctrl_rd_A	381367195	945	0	0
timing0_rd_A	381367195	722	0	0
timing1_rd_A	381367195	812	0	0
timing2_rd_A	381367195	750	0	0
timing3_rd_A	381367195	778	0	0
timing4_rd_A	381367195	685	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	1379	0	0
T88	8606	147	0	0
T89	6589	11	0	0
T90	3958	36	0	0
T91	1416	3	0	0
T92	6471	54	0	0
T93	3274	21	0	0
T94	3446	20	0	0
T95	8185	25	0	0
T96	15171	278	0	0
T97	12853	70	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	5204	0	0
T18	46804	0	0	0
T44	146609	584	0	0
T45	957252	0	0	0
T79	28516	0	0	0
T80	70730	0	0	0
T81	509695	0	0	0
T98	0	161	0	0
T99	0	147	0	0
T100	0	248	0	0
T101	0	192	0	0
T102	0	259	0	0
T103	0	94	0	0
T104	0	124	0	0
T105	0	194	0	0
T106	0	152	0	0
T107	46586	0	0	0
T108	506872	0	0	0
T109	71003	0	0	0
T110	1572	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	766	0	0
T88	8606	52	0	0
T89	6589	9	0	0
T90	3958	14	0	0
T91	1416	3	0	0
T92	6471	38	0	0
T93	3274	20	0	0
T94	3446	7	0	0
T95	8185	25	0	0
T96	15171	119	0	0
T97	12853	36	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	721	0	0
T88	8606	51	0	0
T89	6589	8	0	0
T91	1416	3	0	0
T92	6471	38	0	0
T93	3274	9	0	0
T94	3446	8	0	0
T95	8185	40	0	0
T96	15171	74	0	0
T97	12853	40	0	0
T111	1720	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	2711	0	0
T18	46804	0	0	0
T44	146609	29	0	0
T45	957252	0	0	0
T79	28516	0	0	0
T80	70730	0	0	0
T81	509695	0	0	0
T88	0	385	0	0
T89	0	7	0	0
T90	0	43	0	0
T91	0	2	0	0
T107	46586	0	0	0
T108	506872	0	0	0
T109	71003	0	0	0
T110	1572	0	0	0
T112	0	19	0	0
T113	0	24	0	0
T114	0	5	0	0
T115	0	2	0	0
T116	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	1480	0	0
T50	215807	0	0	0
T117	1189	45	0	0
T118	0	33	0	0
T119	0	64	0	0
T120	0	35	0	0
T121	0	65	0	0
T122	0	60	0	0
T123	0	75	0	0
T124	0	45	0	0
T125	0	66	0	0
T126	0	38	0	0
T127	136258	0	0	0
T128	11411	0	0	0
T129	32503	0	0	0
T130	105382	0	0	0
T131	9489	0	0	0
T132	56116	0	0	0
T133	42699	0	0	0
T134	5156	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	758	0	0
T88	8606	56	0	0
T89	6589	10	0	0
T90	3958	3	0	0
T91	1416	7	0	0
T92	6471	62	0	0
T93	3274	10	0	0
T94	3446	32	0	0
T95	8185	17	0	0
T96	15171	141	0	0
T97	12853	27	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	999	0	0
T88	8606	107	0	0
T89	6589	17	0	0
T90	3958	1	0	0
T91	1416	4	0	0
T92	6471	43	0	0
T93	3274	17	0	0
T94	3446	39	0	0
T95	8185	18	0	0
T96	15171	155	0	0
T97	12853	32	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	748	0	0
T88	8606	64	0	0
T89	6589	14	0	0
T90	3958	7	0	0
T92	6471	59	0	0
T93	3274	7	0	0
T94	3446	10	0	0
T95	8185	41	0	0
T96	15171	112	0	0
T97	12853	34	0	0
T135	8095	10	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	945	0	0
T88	8606	66	0	0
T89	6589	35	0	0
T90	3958	16	0	0
T91	1416	3	0	0
T92	6471	46	0	0
T93	3274	11	0	0
T94	3446	1	0	0
T95	8185	33	0	0
T96	15171	147	0	0
T97	12853	7	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	722	0	0
T88	8606	45	0	0
T89	6589	13	0	0
T90	3958	6	0	0
T91	1416	6	0	0
T92	6471	35	0	0
T93	3274	2	0	0
T94	3446	1	0	0
T95	8185	14	0	0
T96	15171	112	0	0
T97	12853	42	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	812	0	0
T88	8606	77	0	0
T89	6589	27	0	0
T90	3958	17	0	0
T91	1416	8	0	0
T92	6471	17	0	0
T93	3274	14	0	0
T94	3446	7	0	0
T95	8185	20	0	0
T96	15171	109	0	0
T97	12853	31	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	750	0	0
T88	8606	59	0	0
T89	6589	9	0	0
T90	3958	20	0	0
T91	1416	7	0	0
T92	6471	48	0	0
T93	3274	18	0	0
T94	3446	17	0	0
T95	8185	8	0	0
T96	15171	92	0	0
T97	12853	45	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	778	0	0
T88	8606	33	0	0
T89	6589	5	0	0
T90	3958	5	0	0
T91	1416	5	0	0
T92	6471	45	0	0
T93	3274	11	0	0
T94	3446	5	0	0
T95	8185	28	0	0
T96	15171	116	0	0
T97	12853	40	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381367195	685	0	0
T88	8606	40	0	0
T89	6589	12	0	0
T90	3958	7	0	0
T91	1416	4	0	0
T92	6471	56	0	0
T93	3274	15	0	0
T94	3446	1	0	0
T95	8185	29	0	0
T96	15171	113	0	0
T97	12853	30	0	0