Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

165785

1

T4

157

T62

83

T63

90

ack

14614

1

T2

1

T3

30

T4

32

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	616	1			T61	8		T33	4		T72	1
high	37175	1			T2	1		T3	1		T4	34
med	67344	1			T3	7		T4	70		T7	5
sml	74562	1			T3	22		T4	85		T7	11
all_zero	702	1			T61	11		T33	1		T72	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90109

1

T2

1

T3

17

T4

88

auto[1]

90290

1

T3

13

T4

101

T7

8

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123623

1

T2

1

T3

25

T4

141

auto[1]

56776

1

T3

5

T4

48

T62

28

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172738

1

T2

1

T3

13

T4

175

auto[1]

7661

1

T3

17

T4

14

T7

8

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170345

1

T3

17

T4

160

T7

8

auto[1]

10054

1

T2

1

T3

13

T4

29

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171296

1

T2

1

T3

18

T4

161

auto[1]

9103

1

T3

12

T4

28

T7

8

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90109

1

T2

1

T3

17

T4

88

auto[1]

90290

1

T3

13

T4

101

T7

8

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123623

1

T2

1

T3

25

T4

141

auto[1]

56776

1

T3

5

T4

48

T62

28

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172738

1

T2

1

T3

13

T4

175

auto[1]

7661

1

T3

17

T4

14

T7

8

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170345

1

T3

17

T4

160

T7

8

auto[1]

10054

1

T2

1

T3

13

T4

29

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171296

1

T2

1

T3

18

T4

161

auto[1]

9103

1

T3

12

T4

28

T7

8

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

3

1

T245

1

T246

1

T247

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T248

1

T104

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T249

1

T115

1

T250

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

268

1

T4

1

T61

1

T33

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

135

1

T61

2

T33

1

T72

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

152

1

T4

1

T126

1

T142

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

547

1

T4

2

T61

4

T72

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

266

1

T35

1

T33

1

T80

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

288

1

T4

3

T61

5

T33

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

544

1

T4

4

T61

7

T33

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

294

1

T4

1

T61

2

T35

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

241

1

T61

3

T35

1

T33

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

2

1

T251

1

T252

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T253

1

T254

1

T255

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T256

1

T257

1

T249

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	52908	1			T4	43		T62	26		T63	22
write_address_byte	10054	1			T2	1		T3	13		T4	29
read_with_ack	2224	1			T3	5		T60	15		T64	21
read_with_nack	5437	1			T3	12		T4	14		T7	8
stop_byte	9103	1			T3	12		T4	28		T7	8
write_address_byte_nak	5045	1			T4	23		T61	34		T35	6
data_byte_nack	165785	1			T4	157		T62	83		T63	90
stop_byte_nack	5531	1			T4	22		T62	1		T63	1
nakok_byte_nack	83033	1			T4	86		T62	43		T63	53
nakok_addr_byte_nack	2528	1			T4	11		T61	15		T35	2