SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.interrupts_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 45 | 0 | 45 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_acq_stretch | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_stretch_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_cmd_complete | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_cmd_complete_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmt_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmt_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_host_timeout | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_host_timeout_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_nak | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_nak_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_overflow | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_overflow_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_scl_interference | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_scl_interference_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_interference | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_interference_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_unstable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_unstable_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_stretch_timeout | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_stretch_timeout_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_stretch | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_stretch_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_unexp_stop | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_unexp_stop_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 908733 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 520 | 1 | T33 | 1 | T215 | 1 | T41 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 210 | 1 | T33 | 4 | T41 | 5 | T132 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 908580 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 577 | 1 | T33 | 14 | T18 | 1 | T128 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 211 | 1 | T33 | 5 | T41 | 4 | T132 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 192695 | 1 | T1 | 3 | T2 | 19 | T3 | 215 | ||||
auto[1] | 716338 | 1 | T1 | 1 | T3 | 14 | T4 | 17152 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 198 | 1 | T33 | 5 | T41 | 3 | T132 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 97769 | 1 | T1 | 1 | T2 | 19 | T3 | 5 | ||||
auto[1] | 807461 | 1 | T1 | 3 | T3 | 224 | T4 | 16972 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 196 | 1 | T33 | 6 | T41 | 1 | T132 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 908597 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 550 | 1 | T33 | 10 | T132 | 14 | T99 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 211 | 1 | T33 | 5 | T41 | 2 | T132 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 908579 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 553 | 1 | T33 | 7 | T41 | 14 | T132 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 215 | 1 | T33 | 4 | T41 | 4 | T132 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 908647 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 542 | 1 | T33 | 6 | T41 | 10 | T132 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 207 | 1 | T33 | 4 | T41 | 3 | T132 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 908425 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 782 | 1 | T33 | 13 | T80 | 3 | T214 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 221 | 1 | T33 | 6 | T41 | 2 | T132 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 904615 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 595 | 1 | T33 | 11 | T41 | 19 | T132 | 18 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 230 | 1 | T33 | 6 | T41 | 4 | T132 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 904679 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 561 | 1 | T33 | 6 | T41 | 2 | T132 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 214 | 1 | T33 | 8 | T41 | 3 | T132 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 904722 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 542 | 1 | T33 | 28 | T41 | 9 | T132 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 187 | 1 | T33 | 6 | T41 | 6 | T132 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 871819 | 1 | T1 | 4 | T2 | 19 | T3 | 189 | ||||
auto[1] | 33421 | 1 | T3 | 40 | T4 | 189 | T7 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 203 | 1 | T33 | 3 | T41 | 1 | T132 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 908581 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 489 | 1 | T33 | 14 | T132 | 11 | T99 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 212 | 1 | T33 | 4 | T41 | 1 | T132 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5502 | 1 | T1 | 1 | T2 | 19 | T3 | 5 | ||||
auto[1] | 899725 | 1 | T1 | 3 | T3 | 224 | T4 | 18116 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 210 | 1 | T33 | 4 | T41 | 4 | T132 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 908605 | 1 | T1 | 4 | T2 | 19 | T3 | 229 | ||||
auto[1] | 509 | 1 | T33 | 15 | T41 | 10 | T132 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 202 | 1 | T33 | 6 | T41 | 2 | T132 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |