Unified Coverage Report :: Group :: i2c_env_pkg::i2c_status_cg

Group : i2c_env_pkg::i2c_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.status_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group Instance i2c_env_pkg.status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acqempty	2	0	2	100.00	100	1	1	2
cp_acqfull	2	0	2	100.00	100	1	1	2
cp_fmtempty	2	0	2	100.00	100	1	1	2
cp_fmtfull	2	0	2	100.00	100	1	1	2
cp_hostidle	2	0	2	100.00	100	1	1	2
cp_rxempty	2	0	2	100.00	100	1	1	2
cp_rxfull	2	0	2	100.00	100	1	1	2
cp_targetidle	2	0	2	100.00	100	1	1	2
cp_txempty	2	0	2	100.00	100	1	1	2
cp_txfull	2	0	2	100.00	100	1	1	2

Summary for Variable cp_acqempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9656202

1

T1

36

T5

441

T6

148

auto[1]

43571854

1

T1

8386

T2

400

T3

55059

---

Summary for Variable cp_acqfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53213428

1

T1

8422

T2

400

T3

55059

auto[1]

14628

1

T5

147

T8

359

T18

15

---

Summary for Variable cp_fmtempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41944119

1

T2

307

T3

54693

T4

18200

auto[1]

11283937

1

T1

8422

T2

93

T3

366

---

Summary for Variable cp_fmtfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48057403

1

T1

8422

T2

400

T3

55059

auto[1]

5170653

1

T62

251

T63

2243

T61

19

---

Summary for Variable cp_hostidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_hostidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41941182

1

T2

306

T3

54693

T4

18200

auto[1]

11286874

1

T1

8422

T2

94

T3

366

---

Summary for Variable cp_rxempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10602896

1

T2

17

T3

1486

T4

473

auto[1]

42625160

1

T1

8422

T2

383

T3

53573

---

Summary for Variable cp_rxfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53146795

1

T1

8422

T2

400

T3

55059

auto[1]

81261

1

T7

1450

T65

1

T61

83

---

Summary for Variable cp_targetidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_targetidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10857258

1

T1

8421

T5

174

T6

2094

auto[1]

42370798

1

T1

1

T2

400

T3

55059

---

Summary for Variable cp_txempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10776291

1

T1

8252

T6

2094

T9

7497

auto[1]

42451765

1

T1

170

T2

400

T3

55059

---

Summary for Variable cp_txfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52823567

1

T1

8422

T2

400

T3

55059

auto[1]

404489

1

T6

1946

T27

7942

T88

22084