Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45668826	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11190350

1

T1

66

T2

157

T3

14686

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56128778	1			T1	17146		T2	417		T3	55900
values[0x0]	363910	1			T1	102		T2	73		T3	334
values[0x1]	366488	1			T1	82		T2	76		T3	333

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32566013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24293163

1

T1

6430

T2

276

T3

26732

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	201810	1			T2	8		T3	267		T5	4
valid_sources[0x01]	198363	1			T1	1100		T2	28		T3	189
valid_sources[0x02]	207827	1			T3	263		T4	480		T5	3
valid_sources[0x03]	220124	1			T3	160		T4	58		T5	2
valid_sources[0x04]	218906	1			T3	211		T6	31		T7	277
valid_sources[0x05]	223974	1			T2	36		T3	283		T4	39
valid_sources[0x06]	203872	1			T2	11		T3	221		T4	58
valid_sources[0x07]	212810	1			T3	269		T5	9		T6	26
valid_sources[0x08]	207107	1			T3	211		T5	3		T6	19
valid_sources[0x09]	209290	1			T3	251		T5	7		T6	19
valid_sources[0x0a]	232426	1			T3	171		T4	50		T5	4
valid_sources[0x0b]	198983	1			T3	297		T4	97		T5	6
valid_sources[0x0c]	214091	1			T3	203		T5	5		T6	31
valid_sources[0x0d]	199789	1			T3	272		T4	91		T5	4
valid_sources[0x0e]	211927	1			T3	181		T5	4		T6	22
valid_sources[0x0f]	190453	1			T3	290		T5	4		T6	22
valid_sources[0x10]	269634	1			T2	2		T3	177		T5	3
valid_sources[0x11]	199156	1			T3	188		T5	7		T6	21
valid_sources[0x12]	522727	1			T2	1		T3	206		T5	6
valid_sources[0x13]	201606	1			T2	8		T3	365		T6	28
valid_sources[0x14]	208214	1			T2	16		T3	269		T4	35
valid_sources[0x15]	231705	1			T3	173		T4	86		T5	8
valid_sources[0x16]	204536	1			T3	253		T5	2		T6	25
valid_sources[0x17]	210424	1			T2	1		T3	221		T4	102
valid_sources[0x18]	198358	1			T3	310		T5	6		T6	23
valid_sources[0x19]	205353	1			T2	1		T3	237		T4	1362
valid_sources[0x1a]	199270	1			T2	1		T3	227		T4	41
valid_sources[0x1b]	211894	1			T1	749		T3	198		T4	36
valid_sources[0x1c]	208119	1			T2	7		T3	297		T4	102
valid_sources[0x1d]	218391	1			T3	157		T5	5		T6	25
valid_sources[0x1e]	200360	1			T3	315		T5	3		T6	18
valid_sources[0x1f]	200702	1			T3	189		T4	77		T6	27
valid_sources[0x20]	207491	1			T3	198		T4	57		T5	1
valid_sources[0x21]	221799	1			T2	2		T3	312		T5	3
valid_sources[0x22]	208503	1			T3	234		T5	4		T6	24
valid_sources[0x23]	195211	1			T3	178		T5	3		T6	20
valid_sources[0x24]	267088	1			T3	263		T4	40		T5	1
valid_sources[0x25]	208062	1			T1	236		T2	1		T3	174
valid_sources[0x26]	197999	1			T3	161		T5	7		T6	34
valid_sources[0x27]	244044	1			T3	243		T5	2		T6	33
valid_sources[0x28]	222642	1			T2	1		T3	158		T5	2
valid_sources[0x29]	203091	1			T3	261		T5	4		T6	25
valid_sources[0x2a]	207118	1			T2	7		T3	199		T4	58
valid_sources[0x2b]	206788	1			T2	6		T3	222		T4	1348
valid_sources[0x2c]	215290	1			T2	1		T3	237		T5	2
valid_sources[0x2d]	212789	1			T3	334		T5	4		T6	29
valid_sources[0x2e]	198688	1			T3	283		T5	4		T6	31
valid_sources[0x2f]	223527	1			T2	1		T3	162		T5	5
valid_sources[0x30]	210939	1			T3	241		T4	47		T5	2
valid_sources[0x31]	218715	1			T3	194		T5	7		T6	24
valid_sources[0x32]	199815	1			T3	254		T5	7		T6	28
valid_sources[0x33]	208118	1			T3	199		T4	83		T5	2
valid_sources[0x34]	313863	1			T3	164		T5	2		T6	32
valid_sources[0x35]	219513	1			T2	2		T3	264		T4	447
valid_sources[0x36]	271036	1			T3	161		T5	1		T6	35
valid_sources[0x37]	304213	1			T3	205		T5	5		T6	26
valid_sources[0x38]	214772	1			T2	1		T3	265		T4	103
valid_sources[0x39]	195457	1			T3	222		T5	2		T6	23
valid_sources[0x3a]	205717	1			T3	261		T4	32		T5	5
valid_sources[0x3b]	201344	1			T1	783		T3	187		T5	1
valid_sources[0x3c]	322730	1			T3	227		T4	115		T5	5
valid_sources[0x3d]	197773	1			T3	121		T5	3		T6	28
valid_sources[0x3e]	205714	1			T3	252		T4	40		T5	2
valid_sources[0x3f]	198264	1			T3	193		T4	223		T5	2
valid_sources[0x40]	217016	1			T3	218		T4	109		T5	2
valid_sources[0x41]	211378	1			T3	359		T4	44		T5	3
valid_sources[0x42]	201959	1			T3	225		T4	45		T5	2
valid_sources[0x43]	195844	1			T3	205		T4	379		T5	3
valid_sources[0x44]	197883	1			T3	261		T4	50		T5	2
valid_sources[0x45]	211472	1			T3	151		T5	5		T6	34
valid_sources[0x46]	209384	1			T2	4		T3	238		T4	304
valid_sources[0x47]	252889	1			T3	226		T5	4		T6	16
valid_sources[0x48]	198084	1			T3	250		T4	194		T5	4
valid_sources[0x49]	209413	1			T3	185		T4	53		T5	2
valid_sources[0x4a]	207548	1			T3	137		T5	2		T6	24
valid_sources[0x4b]	204131	1			T3	215		T5	3		T6	30
valid_sources[0x4c]	244564	1			T2	55		T3	286		T4	1020
valid_sources[0x4d]	234008	1			T3	154		T4	266		T5	4
valid_sources[0x4e]	193796	1			T3	335		T5	5		T6	31
valid_sources[0x4f]	205650	1			T2	1		T3	139		T4	53
valid_sources[0x50]	196853	1			T3	113		T5	3		T6	28
valid_sources[0x51]	200718	1			T2	1		T3	166		T5	3
valid_sources[0x52]	214527	1			T2	8		T3	233		T5	3
valid_sources[0x53]	358768	1			T2	1		T3	179		T4	250
valid_sources[0x54]	207455	1			T2	3		T3	310		T4	238
valid_sources[0x55]	219641	1			T2	1		T3	219		T5	5
valid_sources[0x56]	209353	1			T3	217		T5	1		T6	21
valid_sources[0x57]	211707	1			T3	300		T5	1		T6	21
valid_sources[0x58]	204948	1			T3	201		T4	80		T5	1
valid_sources[0x59]	212431	1			T2	31		T3	120		T5	7
valid_sources[0x5a]	211223	1			T3	264		T4	736		T5	2
valid_sources[0x5b]	206115	1			T3	364		T4	50		T5	5
valid_sources[0x5c]	226077	1			T3	275		T5	5		T6	33
valid_sources[0x5d]	204644	1			T2	26		T3	153		T4	1539
valid_sources[0x5e]	189740	1			T3	98		T5	4		T6	21
valid_sources[0x5f]	204793	1			T1	1888		T2	3		T3	244
valid_sources[0x60]	203576	1			T2	3		T3	255		T5	1
valid_sources[0x61]	199051	1			T1	415		T3	357		T4	51
valid_sources[0x62]	201347	1			T2	10		T3	248		T4	1199
valid_sources[0x63]	201628	1			T3	252		T5	1		T6	33
valid_sources[0x64]	202951	1			T3	97		T4	43		T5	1
valid_sources[0x65]	238284	1			T2	1		T3	223		T5	4
valid_sources[0x66]	204505	1			T2	3		T3	304		T4	49
valid_sources[0x67]	668568	1			T2	32		T3	203		T5	4
valid_sources[0x68]	391796	1			T2	13		T3	221		T4	40
valid_sources[0x69]	217303	1			T3	211		T5	6		T6	26
valid_sources[0x6a]	204083	1			T3	222		T4	570		T5	5
valid_sources[0x6b]	194801	1			T3	173		T5	2		T6	28
valid_sources[0x6c]	220813	1			T1	1293		T2	7		T3	122
valid_sources[0x6d]	209864	1			T3	114		T4	43		T5	4
valid_sources[0x6e]	226900	1			T3	297		T5	4		T6	26
valid_sources[0x6f]	192026	1			T3	233		T4	40		T6	30
valid_sources[0x70]	334719	1			T3	285		T4	1353		T5	4
valid_sources[0x71]	455317	1			T2	2		T3	170		T5	3
valid_sources[0x72]	237139	1			T3	273		T5	6		T6	21
valid_sources[0x73]	288188	1			T1	1801		T3	165		T5	2
valid_sources[0x74]	216674	1			T3	264		T5	5		T6	23
valid_sources[0x75]	213857	1			T3	266		T4	265		T5	1
valid_sources[0x76]	191283	1			T3	149		T4	51		T5	2
valid_sources[0x77]	209891	1			T3	233		T4	51		T5	3
valid_sources[0x78]	205215	1			T3	189		T4	185		T5	5
valid_sources[0x79]	217969	1			T3	119		T4	35		T5	2
valid_sources[0x7a]	208746	1			T3	170		T5	2		T6	24
valid_sources[0x7b]	351908	1			T2	2		T3	243		T5	4
valid_sources[0x7c]	263671	1			T3	200		T5	3		T6	11
valid_sources[0x7d]	213616	1			T2	18		T3	157		T5	3
valid_sources[0x7e]	198757	1			T3	224		T5	3		T6	31
valid_sources[0x7f]	203029	1			T2	5		T3	190		T5	3
valid_sources[0x80]	196428	1			T3	290		T4	46		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10837145

1

T1

11

T2

58

T3

14276

values[0x0]

all_enables

biggest_size

204132

1

T1

36

T2

51

T3

221

values[0x1]

all_enables

biggest_size

149073

1

T1

19

T2

48

T3

189