Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	365336671	0	0	0
ctrl_rd_A	365336671	1186	0	0
host_fifo_config_rd_A	365336671	3638	0	0
host_nack_handler_timeout_rd_A	365336671	905	0	0
host_timeout_ctrl_rd_A	365336671	803	0	0
intr_enable_rd_A	365336671	2461	0	0
ovrd_rd_A	365336671	1600	0	0
target_fifo_config_rd_A	365336671	1019	0	0
target_id_rd_A	365336671	1049	0	0
target_timeout_ctrl_rd_A	365336671	852	0	0
timeout_ctrl_rd_A	365336671	1046	0	0
timing0_rd_A	365336671	785	0	0
timing1_rd_A	365336671	902	0	0
timing2_rd_A	365336671	938	0	0
timing3_rd_A	365336671	954	0	0
timing4_rd_A	365336671	951	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	1186	0	0
T89	9210	14	0	0
T90	9745	27	0	0
T91	1995	11	0	0
T92	11519	24	0	0
T93	16072	222	0	0
T94	3806	11	0	0
T95	6100	35	0	0
T96	7139	2	0	0
T97	5800	18	0	0
T98	5402	8	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	3638	0	0
T11	72040	0	0	0
T14	21695	0	0	0
T15	9630	0	0	0
T33	708699	71	0	0
T34	32066	0	0	0
T36	22592	0	0	0
T37	33296	0	0	0
T49	5589	0	0	0
T99	0	282	0	0
T100	0	255	0	0
T101	0	264	0	0
T102	0	92	0	0
T103	0	86	0	0
T104	0	407	0	0
T105	0	250	0	0
T106	0	113	0	0
T107	0	239	0	0
T108	159679	0	0	0
T109	38302	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	905	0	0
T89	9210	23	0	0
T90	9745	41	0	0
T91	1995	4	0	0
T92	11519	12	0	0
T93	16072	102	0	0
T94	3806	24	0	0
T95	6100	43	0	0
T96	7139	25	0	0
T97	5800	39	0	0
T98	5402	6	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	803	0	0
T89	9210	22	0	0
T90	9745	11	0	0
T91	1995	6	0	0
T92	11519	10	0	0
T93	16072	92	0	0
T94	3806	14	0	0
T95	6100	45	0	0
T96	7139	16	0	0
T97	5800	31	0	0
T98	5402	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	2461	0	0
T11	72040	0	0	0
T14	21695	0	0	0
T15	9630	0	0	0
T33	708699	16	0	0
T34	32066	0	0	0
T36	22592	0	0	0
T37	33296	0	0	0
T49	5589	0	0	0
T89	0	17	0	0
T99	0	10	0	0
T104	0	70	0	0
T108	159679	0	0	0
T109	38302	0	0	0
T110	0	31	0	0
T111	0	20	0	0
T112	0	36	0	0
T113	0	27	0	0
T114	0	7	0	0
T115	0	28	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	1600	0	0
T12	147616	0	0	0
T13	133861	0	0	0
T40	8722	0	0	0
T50	16161	0	0	0
T71	0	54	0	0
T87	2703	62	0	0
T116	0	82	0	0
T117	0	48	0	0
T118	0	22	0	0
T119	0	30	0	0
T120	0	54	0	0
T121	0	52	0	0
T122	0	44	0	0
T123	0	16	0	0
T124	952	0	0	0
T125	134314	0	0	0
T126	372384	0	0	0
T127	45461	0	0	0
T128	36613	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	1019	0	0
T89	9210	3	0	0
T90	9745	8	0	0
T91	1995	10	0	0
T92	11519	29	0	0
T93	16072	122	0	0
T94	3806	29	0	0
T95	6100	64	0	0
T96	7139	3	0	0
T97	5800	38	0	0
T98	5402	14	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	1049	0	0
T89	9210	7	0	0
T90	9745	37	0	0
T91	1995	21	0	0
T92	11519	27	0	0
T93	16072	146	0	0
T94	3806	7	0	0
T95	6100	28	0	0
T96	7139	16	0	0
T97	5800	35	0	0
T98	5402	8	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	852	0	0
T89	9210	12	0	0
T90	9745	21	0	0
T91	1995	8	0	0
T92	11519	11	0	0
T93	16072	103	0	0
T94	3806	31	0	0
T95	6100	37	0	0
T96	7139	5	0	0
T97	5800	6	0	0
T98	5402	15	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	1046	0	0
T89	9210	7	0	0
T90	9745	22	0	0
T91	1995	10	0	0
T92	11519	1	0	0
T93	16072	155	0	0
T94	3806	31	0	0
T95	6100	63	0	0
T96	7139	11	0	0
T97	5800	18	0	0
T98	5402	8	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	785	0	0
T89	9210	14	0	0
T90	9745	9	0	0
T91	1995	1	0	0
T92	11519	9	0	0
T93	16072	120	0	0
T94	3806	7	0	0
T95	6100	68	0	0
T97	5800	10	0	0
T98	5402	15	0	0
T129	8260	49	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	902	0	0
T89	9210	15	0	0
T90	9745	8	0	0
T91	1995	1	0	0
T92	11519	16	0	0
T93	16072	86	0	0
T94	3806	23	0	0
T95	6100	59	0	0
T96	7139	9	0	0
T97	5800	41	0	0
T129	8260	55	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	938	0	0
T89	9210	27	0	0
T90	9745	17	0	0
T91	1995	11	0	0
T92	11519	11	0	0
T93	16072	118	0	0
T94	3806	32	0	0
T95	6100	49	0	0
T96	7139	5	0	0
T97	5800	58	0	0
T98	5402	9	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	954	0	0
T89	9210	21	0	0
T90	9745	42	0	0
T91	1995	11	0	0
T92	11519	8	0	0
T93	16072	109	0	0
T94	3806	17	0	0
T95	6100	30	0	0
T96	7139	7	0	0
T97	5800	28	0	0
T129	8260	73	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365336671	951	0	0
T89	9210	18	0	0
T90	9745	7	0	0
T91	1995	16	0	0
T92	11519	24	0	0
T93	16072	106	0	0
T94	3806	16	0	0
T95	6100	52	0	0
T96	7139	6	0	0
T97	5800	50	0	0
T129	8260	58	0	0