Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

159476

1

T1

8

T3

118

T6

598

ack

13844

1

T1

2

T3

12

T5

10

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	603	1			T6	3		T62	3		T36	13
high	35500	1			T1	2		T3	45		T5	1
med	64896	1			T1	5		T3	49		T5	3
sml	71647	1			T1	3		T3	36		T5	6
all_zero	674	1			T6	1		T10	1		T62	4

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86559

1

T1

3

T3

69

T5

6

auto[1]

86761

1

T1

7

T3

61

T5

4

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118550

1

T1

9

T3

93

T5

10

auto[1]

54770

1

T1

1

T3

37

T6

189

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166108

1

T1

10

T3

130

T5

5

auto[1]

7212

1

T5

5

T6

6

T10

11

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163692

1

T1

8

T3

118

T5

5

auto[1]

9628

1

T1

2

T3

12

T5

5

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164670

1

T1

10

T3

118

T5

5

auto[1]

8650

1

T3

12

T5

5

T6

8

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86559

1

T1

3

T3

69

T5

6

auto[1]

86761

1

T1

7

T3

61

T5

4

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118550

1

T1

9

T3

93

T5

10

auto[1]

54770

1

T1

1

T3

37

T6

189

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166108

1

T1

10

T3

130

T5

5

auto[1]

7212

1

T5

5

T6

6

T10

11

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163692

1

T1

8

T3

118

T5

5

auto[1]

9628

1

T1

2

T3

12

T5

5

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164670

1

T1

10

T3

118

T5

5

auto[1]

8650

1

T3

12

T5

5

T6

8

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T36

1

T48

1

T256

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T257

1

T258

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T62

1

T259

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

256

1

T36

5

T55

1

T96

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

146

1

T62

1

T36

5

T55

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

129

1

T6

1

T36

4

T55

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

501

1

T10

1

T62

3

T36

13

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

285

1

T10

1

T62

2

T36

10

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

248

1

T62

1

T36

5

T55

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

525

1

T6

1

T10

1

T62

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

256

1

T36

7

T96

1

T107

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

267

1

T6

1

T62

1

T36

7

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T260

1

T259

1

T261

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T262

1

T263

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T264

1

T265

1

T165

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50506	1			T1	2		T3	36		T6	195
write_address_byte	9628	1			T1	2		T3	12		T5	5
read_with_ack	2065	1			T6	2		T10	8		T33	18
read_with_nack	5147	1			T5	5		T6	4		T10	3
stop_byte	8650	1			T3	12		T5	5		T6	8
write_address_byte_nak	4798	1			T6	8		T10	4		T62	18
data_byte_nack	159476	1			T1	8		T3	118		T6	598
stop_byte_nack	5261	1			T3	12		T6	5		T10	4
nakok_byte_nack	79882	1			T1	5		T3	58		T6	293
nakok_addr_byte_nack	2395	1			T6	4		T10	3		T62	14