Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50893089	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11801589

1

T1

239

T2

13

T3

1495

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	61944366	1			T1	637		T2	14		T3	2830
values[0x0]	374877	1			T1	104		T2	8		T3	108
values[0x1]	375435	1			T1	104		T2	8		T3	113

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36314249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26380429

1

T1

433

T2

20

T3

1834

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	216438	1			T1	6		T6	366		T7	3
valid_sources[0x01]	215504	1			T1	1		T2	1		T4	5
valid_sources[0x02]	223735	1			T1	5		T2	1		T4	4
valid_sources[0x03]	229809	1			T1	1		T5	2493		T6	446
valid_sources[0x04]	240625	1			T1	8		T6	431		T10	77
valid_sources[0x05]	206623	1			T1	2		T6	400		T10	70
valid_sources[0x06]	240132	1			T1	6		T6	398		T9	25
valid_sources[0x07]	224302	1			T1	4		T6	367		T10	68
valid_sources[0x08]	225264	1			T1	2		T6	364		T10	101
valid_sources[0x09]	266844	1			T1	6		T4	1		T6	400
valid_sources[0x0a]	231041	1			T1	6		T6	433		T10	82
valid_sources[0x0b]	240564	1			T1	2		T6	420		T8	60
valid_sources[0x0c]	225309	1			T1	2		T4	2		T6	403
valid_sources[0x0d]	240951	1			T1	4		T5	1		T6	427
valid_sources[0x0e]	222409	1			T1	2		T6	394		T7	2
valid_sources[0x0f]	227058	1			T1	3		T6	346		T9	1
valid_sources[0x10]	211482	1			T4	1		T6	394		T7	1
valid_sources[0x11]	261923	1			T1	1		T6	376		T9	7
valid_sources[0x12]	216369	1			T1	1		T4	4		T6	352
valid_sources[0x13]	223466	1			T1	8		T6	364		T7	2
valid_sources[0x14]	215353	1			T1	3		T4	1		T6	367
valid_sources[0x15]	232299	1			T1	6		T6	414		T10	79
valid_sources[0x16]	214393	1			T1	2		T4	8		T6	418
valid_sources[0x17]	227810	1			T1	5		T4	2		T6	501
valid_sources[0x18]	221041	1			T1	2		T6	440		T7	2
valid_sources[0x19]	216734	1			T1	9		T6	426		T7	2
valid_sources[0x1a]	209910	1			T1	1		T2	1		T4	2
valid_sources[0x1b]	270207	1			T1	5		T4	1		T6	432
valid_sources[0x1c]	658151	1			T2	1		T6	360		T10	91
valid_sources[0x1d]	218461	1			T1	1		T4	3		T6	404
valid_sources[0x1e]	242825	1			T1	2		T6	399		T7	1
valid_sources[0x1f]	241126	1			T1	3		T6	495		T9	8
valid_sources[0x20]	234424	1			T1	4		T4	1		T6	408
valid_sources[0x21]	213994	1			T1	4		T5	1394		T6	421
valid_sources[0x22]	227331	1			T5	2194		T6	434		T10	87
valid_sources[0x23]	232150	1			T1	4		T6	401		T9	5
valid_sources[0x24]	232826	1			T1	6		T6	428		T10	79
valid_sources[0x25]	222765	1			T1	4		T4	2		T6	394
valid_sources[0x26]	211822	1			T1	2		T6	392		T10	78
valid_sources[0x27]	223827	1			T4	1		T6	432		T10	81
valid_sources[0x28]	239121	1			T1	4		T6	367		T9	10
valid_sources[0x29]	223162	1			T1	4		T6	441		T9	51
valid_sources[0x2a]	213951	1			T1	2		T6	367		T9	35
valid_sources[0x2b]	216685	1			T1	3		T6	380		T10	95
valid_sources[0x2c]	236853	1			T1	5		T4	3		T6	412
valid_sources[0x2d]	220339	1			T1	4		T2	1		T4	2
valid_sources[0x2e]	1142645	1			T1	9		T6	409		T9	10
valid_sources[0x2f]	224406	1			T1	6		T6	426		T9	11
valid_sources[0x30]	219679	1			T1	1		T6	275		T10	65
valid_sources[0x31]	222985	1			T1	2		T6	406		T10	82
valid_sources[0x32]	213261	1			T1	10		T4	1		T6	364
valid_sources[0x33]	227963	1			T1	4		T6	388		T10	81
valid_sources[0x34]	209772	1			T1	6		T4	3		T6	410
valid_sources[0x35]	214694	1			T1	2		T5	1		T6	408
valid_sources[0x36]	230474	1			T1	2		T6	416		T9	23
valid_sources[0x37]	226626	1			T1	3		T6	424		T10	101
valid_sources[0x38]	228329	1			T1	3		T6	431		T10	105
valid_sources[0x39]	210735	1			T1	7		T6	468		T10	76
valid_sources[0x3a]	377656	1			T6	479		T7	3		T10	69
valid_sources[0x3b]	227967	1			T1	4		T6	406		T10	80
valid_sources[0x3c]	224112	1			T1	7		T4	2		T6	464
valid_sources[0x3d]	212436	1			T1	2		T4	5		T6	377
valid_sources[0x3e]	840704	1			T1	3		T6	349		T7	1
valid_sources[0x3f]	234059	1			T1	5		T6	363		T10	86
valid_sources[0x40]	226203	1			T1	3		T6	409		T10	99
valid_sources[0x41]	219444	1			T6	381		T7	1		T10	88
valid_sources[0x42]	227456	1			T1	5		T4	2		T6	395
valid_sources[0x43]	224952	1			T1	2		T6	339		T10	93
valid_sources[0x44]	214091	1			T1	2		T2	1		T5	1
valid_sources[0x45]	216627	1			T1	6		T2	1		T6	366
valid_sources[0x46]	212346	1			T1	5		T4	2		T6	389
valid_sources[0x47]	208137	1			T1	1		T6	399		T10	84
valid_sources[0x48]	219999	1			T1	7		T6	404		T7	3
valid_sources[0x49]	228890	1			T1	4		T2	1		T6	384
valid_sources[0x4a]	226315	1			T1	2		T6	386		T10	75
valid_sources[0x4b]	214571	1			T1	1		T6	396		T7	1
valid_sources[0x4c]	221577	1			T1	6		T6	447		T7	1
valid_sources[0x4d]	399990	1			T1	1		T6	409		T10	92
valid_sources[0x4e]	277464	1			T1	7		T5	129		T6	367
valid_sources[0x4f]	234189	1			T1	3		T4	2		T6	340
valid_sources[0x50]	251141	1			T6	403		T7	1		T10	73
valid_sources[0x51]	218208	1			T1	1		T6	441		T9	9
valid_sources[0x52]	225278	1			T1	2		T6	387		T10	86
valid_sources[0x53]	233729	1			T1	3		T6	382		T10	88
valid_sources[0x54]	225256	1			T1	3		T2	1		T6	362
valid_sources[0x55]	226014	1			T1	4		T6	490		T10	88
valid_sources[0x56]	225178	1			T1	2		T4	1		T6	328
valid_sources[0x57]	216101	1			T1	4		T2	1		T6	353
valid_sources[0x58]	322290	1			T1	5		T4	4		T6	370
valid_sources[0x59]	227886	1			T1	1		T6	398		T9	8
valid_sources[0x5a]	224131	1			T1	2		T4	3		T6	435
valid_sources[0x5b]	228746	1			T1	3		T6	401		T10	92
valid_sources[0x5c]	232687	1			T1	3		T2	1		T6	370
valid_sources[0x5d]	229525	1			T1	4		T6	318		T7	4
valid_sources[0x5e]	231217	1			T1	1		T2	1		T4	3
valid_sources[0x5f]	217822	1			T1	7		T6	405		T7	2
valid_sources[0x60]	217791	1			T1	3		T4	2		T6	452
valid_sources[0x61]	322607	1			T1	4		T6	404		T10	78
valid_sources[0x62]	217886	1			T1	3		T6	376		T7	3
valid_sources[0x63]	436151	1			T1	5		T5	1		T6	472
valid_sources[0x64]	223639	1			T4	1		T6	438		T10	101
valid_sources[0x65]	225564	1			T1	1		T6	380		T9	25
valid_sources[0x66]	226926	1			T6	344		T7	3		T10	75
valid_sources[0x67]	215587	1			T1	1		T4	1		T6	389
valid_sources[0x68]	216056	1			T1	1		T6	418		T7	1
valid_sources[0x69]	217402	1			T1	3		T6	424		T7	2
valid_sources[0x6a]	221211	1			T1	1		T4	2		T6	357
valid_sources[0x6b]	226818	1			T1	2		T6	399		T7	2
valid_sources[0x6c]	230930	1			T1	4		T6	415		T7	4
valid_sources[0x6d]	234247	1			T1	2		T4	4		T6	377
valid_sources[0x6e]	207862	1			T1	3		T6	345		T10	81
valid_sources[0x6f]	217232	1			T1	3		T5	1436		T6	421
valid_sources[0x70]	217648	1			T1	4		T6	389		T10	72
valid_sources[0x71]	236938	1			T1	2		T2	1		T6	410
valid_sources[0x72]	229780	1			T1	2		T6	402		T10	97
valid_sources[0x73]	218463	1			T1	3		T6	421		T10	96
valid_sources[0x74]	227941	1			T1	2		T4	2		T5	1091
valid_sources[0x75]	240277	1			T1	6		T4	6		T6	372
valid_sources[0x76]	257126	1			T1	1		T6	412		T10	67
valid_sources[0x77]	228622	1			T2	1		T6	354		T9	16
valid_sources[0x78]	240237	1			T1	2		T6	403		T9	8
valid_sources[0x79]	439728	1			T1	3		T6	461		T10	75
valid_sources[0x7a]	219969	1			T1	4		T5	1		T6	387
valid_sources[0x7b]	303791	1			T1	4		T4	3		T6	394
valid_sources[0x7c]	233837	1			T6	453		T7	3		T9	11
valid_sources[0x7d]	230390	1			T1	9		T6	416		T10	72
valid_sources[0x7e]	213581	1			T1	2		T6	433		T9	1
valid_sources[0x7f]	213221	1			T6	334		T7	3		T10	77
valid_sources[0x80]	223558	1			T1	4		T6	386		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11443625

1

T1

94

T2

6

T3

1348

values[0x0]

all_enables

biggest_size

208364

1

T1

76

T2

6

T3

75

values[0x1]

all_enables

biggest_size

149600

1

T1

69

T2

1

T3

72