Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	390651306	0	0	0
ctrl_rd_A	390651306	2438	0	0
host_fifo_config_rd_A	390651306	4486	0	0
host_nack_handler_timeout_rd_A	390651306	1435	0	0
host_timeout_ctrl_rd_A	390651306	1259	0	0
intr_enable_rd_A	390651306	4294	0	0
ovrd_rd_A	390651306	2558	0	0
target_fifo_config_rd_A	390651306	1354	0	0
target_id_rd_A	390651306	1996	0	0
target_timeout_ctrl_rd_A	390651306	1365	0	0
timeout_ctrl_rd_A	390651306	1663	0	0
timing0_rd_A	390651306	1268	0	0
timing1_rd_A	390651306	1320	0	0
timing2_rd_A	390651306	1342	0	0
timing3_rd_A	390651306	1382	0	0
timing4_rd_A	390651306	1315	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	2438	0	0
T86	15372	43	0	0
T87	15943	344	0	0
T88	6319	44	0	0
T89	7554	7	0	0
T90	3203	41	0	0
T91	7058	7	0	0
T92	3771	87	0	0
T93	6722	50	0	0
T94	14148	168	0	0
T95	11898	7	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	4486	0	0
T14	48294	0	0	0
T28	102750	0	0	0
T29	11626	0	0	0
T55	377997	123	0	0
T96	521037	116	0	0
T97	0	312	0	0
T98	0	156	0	0
T99	0	131	0	0
T100	0	121	0	0
T101	0	235	0	0
T102	0	140	0	0
T103	0	333	0	0
T104	0	296	0	0
T105	27440	0	0	0
T106	115631	0	0	0
T107	282020	0	0	0
T108	48909	0	0	0
T109	380892	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1435	0	0
T86	15372	36	0	0
T87	15943	94	0	0
T88	6319	83	0	0
T89	7554	23	0	0
T90	3203	20	0	0
T91	7058	10	0	0
T92	3771	29	0	0
T93	6722	86	0	0
T94	14148	40	0	0
T95	11898	11	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1259	0	0
T86	15372	37	0	0
T87	15943	111	0	0
T88	6319	63	0	0
T89	7554	10	0	0
T90	3203	15	0	0
T91	7058	13	0	0
T92	3771	16	0	0
T93	6722	32	0	0
T94	14148	39	0	0
T95	11898	36	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	4294	0	0
T67	19400	0	0	0
T76	324203	0	0	0
T77	283225	0	0	0
T97	171563	11	0	0
T100	0	61	0	0
T103	0	10	0	0
T110	0	25	0	0
T111	0	30	0	0
T112	0	31	0	0
T113	0	44	0	0
T114	0	27	0	0
T115	0	10	0	0
T116	0	21	0	0
T117	81468	0	0	0
T118	14704	0	0	0
T119	26728	0	0	0
T120	201771	0	0	0
T121	213784	0	0	0
T122	4941	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	2558	0	0
T2	1164	39	0	0
T3	28777	0	0	0
T4	13713	0	0	0
T5	136677	0	0	0
T6	206583	0	0	0
T7	6829	0	0	0
T8	9672	0	0	0
T9	125642	0	0	0
T10	197050	0	0	0
T11	69924	0	0	0
T123	0	22	0	0
T124	0	51	0	0
T125	0	52	0	0
T126	0	38	0	0
T127	0	53	0	0
T128	0	38	0	0
T129	0	58	0	0
T130	0	83	0	0
T131	0	44	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1354	0	0
T86	15372	12	0	0
T87	15943	96	0	0
T88	6319	55	0	0
T89	7554	7	0	0
T90	3203	19	0	0
T91	7058	5	0	0
T92	3771	25	0	0
T93	6722	80	0	0
T94	14148	67	0	0
T95	11898	19	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1996	0	0
T86	15372	45	0	0
T87	15943	284	0	0
T88	6319	86	0	0
T89	7554	4	0	0
T90	3203	6	0	0
T91	7058	3	0	0
T92	3771	33	0	0
T93	6722	68	0	0
T94	14148	122	0	0
T95	11898	12	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1365	0	0
T86	15372	32	0	0
T87	15943	92	0	0
T88	6319	93	0	0
T89	7554	18	0	0
T90	3203	16	0	0
T91	7058	30	0	0
T92	3771	28	0	0
T93	6722	41	0	0
T94	14148	39	0	0
T132	4848	6	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1663	0	0
T86	15372	72	0	0
T87	15943	145	0	0
T88	6319	34	0	0
T89	7554	6	0	0
T90	3203	13	0	0
T91	7058	6	0	0
T92	3771	23	0	0
T93	6722	62	0	0
T94	14148	109	0	0
T95	11898	15	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1268	0	0
T86	15372	23	0	0
T87	15943	106	0	0
T88	6319	29	0	0
T89	7554	1	0	0
T90	3203	14	0	0
T91	7058	3	0	0
T92	3771	22	0	0
T93	6722	30	0	0
T94	14148	21	0	0
T95	11898	27	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1320	0	0
T86	15372	41	0	0
T87	15943	121	0	0
T88	6319	10	0	0
T89	7554	5	0	0
T90	3203	27	0	0
T91	7058	11	0	0
T92	3771	19	0	0
T93	6722	19	0	0
T94	14148	63	0	0
T95	11898	3	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1342	0	0
T86	15372	35	0	0
T87	15943	133	0	0
T88	6319	20	0	0
T89	7554	11	0	0
T90	3203	4	0	0
T91	7058	23	0	0
T92	3771	5	0	0
T93	6722	68	0	0
T94	14148	53	0	0
T95	11898	19	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1382	0	0
T86	15372	70	0	0
T87	15943	126	0	0
T88	6319	30	0	0
T89	7554	10	0	0
T90	3203	17	0	0
T91	7058	13	0	0
T92	3771	24	0	0
T93	6722	37	0	0
T94	14148	61	0	0
T95	11898	7	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390651306	1315	0	0
T86	15372	43	0	0
T87	15943	118	0	0
T88	6319	34	0	0
T89	7554	17	0	0
T90	3203	10	0	0
T91	7058	22	0	0
T92	3771	13	0	0
T93	6722	36	0	0
T94	14148	52	0	0
T95	11898	9	0	0