Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

155562

1

T9

217

T10

8

T30

23

ack

14399

1

T2

1

T7

38

T8

41

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	594	1			T8	1		T30	1		T31	1
high	35002	1			T2	1		T7	6		T8	3
med	63271	1			T7	4		T8	5		T9	89
sml	70473	1			T7	28		T8	32		T9	114
all_zero	621	1			T9	3		T30	1		T38	6

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84532

1

T2

1

T7

14

T8

21

auto[1]

85429

1

T7

24

T8

20

T9

129

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116689

1

T2

1

T7

25

T8

31

auto[1]

53272

1

T7

13

T8

10

T9

66

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162446

1

T2

1

T7

13

T8

16

auto[1]

7515

1

T7

25

T8

25

T9

18

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160127

1

T7

25

T8

25

T9

218

auto[1]

9834

1

T2

1

T7

13

T8

16

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161112

1

T2

1

T7

26

T8

26

auto[1]

8849

1

T7

12

T8

15

T9

36

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84532

1

T2

1

T7

14

T8

21

auto[1]

85429

1

T7

24

T8

20

T9

129

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116689

1

T2

1

T7

25

T8

31

auto[1]

53272

1

T7

13

T8

10

T9

66

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162446

1

T2

1

T7

13

T8

16

auto[1]

7515

1

T7

25

T8

25

T9

18

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160127

1

T7

25

T8

25

T9

218

auto[1]

9834

1

T2

1

T7

13

T8

16

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161112

1

T2

1

T7

26

T8

26

auto[1]

8849

1

T7

12

T8

15

T9

36

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T42

1

T272

1

T273

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T38

1

T274

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T275

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

288

1

T38

1

T80

2

T81

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

136

1

T38

2

T42

1

T80

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

121

1

T38

2

T42

1

T80

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

506

1

T9

4

T38

9

T80

5

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

279

1

T9

1

T38

3

T42

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

259

1

T9

2

T38

1

T80

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

479

1

T9

2

T38

2

T41

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

263

1

T9

2

T38

3

T80

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

245

1

T38

1

T80

1

T43

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T276

1

T120

1

T277

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T278

1

T279

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T9

1

T47

1

T280

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	49336	1			T9	57		T30	7		T31	46
write_address_byte	9834	1			T2	1		T7	13		T8	16
read_with_ack	2201	1			T7	13		T8	10		T30	1
read_with_nack	5314	1			T7	12		T8	15		T9	18
stop_byte	8849	1			T7	12		T8	15		T9	36
write_address_byte_nak	4773	1			T9	27		T10	3		T30	2
data_byte_nack	155562	1			T9	217		T10	8		T30	23
stop_byte_nack	5301	1			T9	29		T10	1		T30	1
nakok_byte_nack	78272	1			T9	114		T10	8		T30	12
nakok_addr_byte_nack	2390	1			T9	14		T10	3		T30	1